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参数资料
| 型号： | W3HG2128M72AEF665F2MBG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 2/18页 |
| 文件大小： | 348K |
| 代理商： | W3HG2128M72AEF665F2MBG |
10
W3HG2128M72AEF-Fx
June 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
NOTES:
1.
133 MHz for PC2-4200 and 166MHZ for PC2-5300
2.
Measured with SSC disabled.
3.
Measured differentially through the range of 0.175V to 0.525V.
4.
The crossing point must meet the absolute and relative crossing point
specication simultaneously.
5.
VCROSS_REL_(MIN) and VCROSS_REL_(MAX) are derived using the following
calculations: Min = 0.5 (Vhavg -0.710) + 0.250; and Max = 0.5 (Vhavg - 0.710) + 0.550, where
Vhavg is the average of VSCK-HIGHM.
6.
Measured with a single-ended input voltage of 1V.
7.
Applies to reference clocks SCK and SCK#.
8.
Difference between SCK and SCK# input.
9.
T1 = |Tdatapath - Tclockpath| (excluding PLL loop delays). This
parameter is not a direct clock output parameter but it indirectly
determines the clock output parameter TREF-JITTER.
10.
The net transport delay is the difference in time of ight between
associated data and clock paths. The data path is dened from
the reference clock source, through the TX , to data arrival at the
data sampling point in the RX. The clock path is dened from the
reference clock source to clock arrival at the sampling point. The
path delays are caused by copper trace routes, on-chip routing, on-
chip buffering, etc. They include the time-of-ight of interpolators or
other clock adjustment mechanisms. They do not include the phase
delays caused by nite PLL loop bandwidth because these delays are
modeled by the PLL transfer functions.
11.
Direct measurement of phase jitter records over 1016 periods is
impractical. It is expected that the jitter will be measured over a
smaller, yet statistically signicant, sample size and total jitter at 1016
samples extrapolated from an estimated of the sigma of the random
jitter components.
12.
Measured with SSC enabled on reference clock generator.
13.
As measured after the phase jitter lter. This number is separate
from the receiver jitter budget that is dened by the TRXTotal -Min
parameters.
REFERENCE CLOCK INPUT SPECIFICATIONS
Parameter
Symbol
Values
Unit
Notes
Min
Max
Reference clock frequency
fSCK
133.33
200
MHz
1, 2
Rise time, fall time
TSCK-RISE, TSCK-FALL
175
700
ps
3
Voltage high
VSCK-HIGH
600
850
mV
Voltage low
VSCK-LOW
-150
mV
Absolute crossing point
VCROSS-ABS
250
550
mV
4
Relative crossing point
VCROSS-REL
calculated
4, 5
Percent mismatch between rise and fall times
TSCK-RISE-FALL-MATCH
-10
%
Duty cycle of reference clock
TSCK-DUTYCYCLE
40
60
%
Clock leakage current
Il-CK
-10
10
A
6, 7
Clock input capacitance
Cl-CK
0.5
2
pF
7
Clock input capacitance delta
Cl_CK (D)
-0.25
0.25
pF
8
Transport delay
T1
5
ns
9, 10
Phase jitter sample size
NSAMPLE
1016
Periods
11
Reference clock jitter, ltered
TREF-JITTER
40
ps
12, 13
Reference clock deterministic jitter
TREF-DJ
TBD
ps
VTT CURRENTS
Parameter
Symbol
Typ
Max
Unit
Idle current, DDR2 SDRAM device power down
ITT1
500
700
mA
Active power, 50% DDR2 BW
ITT2
500
700
mA
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