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参数资料
| 型号： | W3HG2128M72AEF665F2MBG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 18/18页 |
| 文件大小： | 348K |
| 代理商： | W3HG2128M72AEF665F2MBG |
9
W3HG2128M72AEF-Fx
June 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
Timing Parameters
Parameter
Symbol
Min
Typical
Max
Unit
Notes
El assertion pass-through timing
t
El Propagate
4
CK
El de assertion pass-through timing
t
EID
Bitlock
CK
2
El assertion duration
t
EI
100
CK
1, 2
FBD command to DDR2 clock out that latches command
8.1
ns
3
FBD command to DDR2 WRITE
TBD
ns
DDR2 READ to FBD (last FBDIMM)
5.0
ns
4
Resample pass-through time
1.075
ns
Resynch pass-through time
2.075
ns
Bitlock interval
t
Bitlock
119
frames
1
Framelock interval
t
Framelock
154
frames
1
Note: 1. Dened in FBDIMM architecture and protocol specication.
2. Clocks dened as core clocks - 2x SCK input
3. For DDR2-667 (PC2-5300), this is measured from the beginning of the frame at the southbound input to the DDR2 clock output that latches the rst command of a frame
to the DDR2 SDRAM devices
4. For DDR2-667 (PC2-5300), this is measured from the latest DQS input to the AMB to the start of the matching data frame at the northbound FBDIMM outputs.
AMB IDD SPECIFICATIONS AND CONDITIONS
Symbol
Condition
806
665
534
Units
Idd_Idle_0
Idle Current, single or last DIMM, LO state, idle (0 BW), Primary channel enabled,
Secondary Channel disabled , CKE high. Command and address lines stable. DRAM
clock active
@1.5v
TBD
2.6
2.2
A
@1.8v
TBD
0.9
A
Idd_Idle_1
Idle Current, rst DIMM, LO state, idle (0 BW), Primary and Secondary channels
enabled CKE high, Command and address lines stable. DRAM clock active.
@1.5v
TBD
3.4
3.0
A
@1.8v
TBD
0.9
A
Idd_Active_1
Active Power, LO state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary
channels enabled. DRAM clock active, CKE high.
@1.5v
TBD
3.9
3.4
A
@1.8v
TBD
1.7
A
Idd_Active_2
Active Power, LO state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary
channels enabled. DRAM clock active, CKE high.
@1.5v
TBD
3.7
3.2
A
@1.8v
TBD
0.9
A
Idd_Training
Training, Primary and Secondary channels enabled. 100% toggle on all channel lanes
DRAMs idle. 0BW. CKE high, Command and address lines stable. DRAM clock active.
@1.5v
TBD
4.0
3.5
A
@1.8v
TBD
0.9
A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER534AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER665AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER806AD7XG | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
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