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参数资料
| 型号： | W3HG2128M72AEF665F2MBG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, DMA240 |
| 封装： | ROHS COMPLIANT, DIMM-240 |
| 文件页数： | 5/18页 |
| 文件大小： | 348K |
| 代理商： | W3HG2128M72AEF665F2MBG |
13
W3HG2128M72AEF-Fx
June 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DIFFERENTIAL RECEIVER INPUT SPECIFICATIONS
Parameter
Values
Units
Comments
Symbol
Min
Max
Differential peak-to-peak input voltage for large voltage swing
VRX-DIFF p-p
170
TBD
mV
EQ 5, Note 1
Maximum single-ended voltage in EI condition
VRX-IDLE-SE
—
75
mV
2, 3
Maximum single-ended voltage in El condition (DC only)
VRX-IDLE-SE-DC
—
50
mV
2, 3
Maximum peak-to-peak differential voltage in El condition
VRX-IDLE-DIFF p-p
—
65
mV
3
Sinlge-ended voltage (w.r.t. Vss on D+/D-
VRX-SE
-300
900
mV
4
Single-pulse peak differential input voltage
VRX-DIFF-PULSE
85
—
mV
4, 5
Amplitude ratio between adjacent symbols
VRX-DIFF-ADJ-RATIO
—
TBD
—
4, 6
Maximum RX inherent timing error, 3.2 and 4.0 Gb/s
TRX-TJ-MAX
—
0.4
UI
4, 7, 8
Maximum RX inherent deterministic timing error, 3.2 and 4.8 Gb/s
TRX-TJ-MAX 4.8
—
TBD
UI
4, 7, 8
Single-pulse width as zero-voltage crossing
VRX-DJ-DD
—
0.3
UI
4, 7, 8, 9
Single-pulse width at minimum-level crossing
VRX-DJ-DD-4.8
—
TBD
UI
4, 7, 8, 9
Differential RX input rise/fall time
TRX-PW-ZC
0.55
—
UI
4, 5
Common mode of the input voltage
TRX-PW-ML
0.2
—UI
4, 5
Differential RX outout rise/fall time
TRX-RISE TRX-FALL
50
—ps
20-80% voltage
Common mode of input voltage
VRX-CM
120
400
mV
EQ6, Note1, 10
AC peak-to-peak common mode of input voltage
VRX-CM-H-ACp-p
—
270
mV
EQ7, Note1
Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p
VRX-CM-EH-RATOP
—45
%11
Differential return loss
RLRX-DIFF
9—
dB
Meas. 0.1-2.4GHz, Note 12
Common mode return loss
RLRX-CM
6—
dB
Meas. 0.1-2.4GHz, Note 12
RX termination impedance
RRX
41
55
13
D+/D- RX Impedance difference
RRX-MATCH-DC
—4
%
EQ 8
Lane-to lane PCB skew at RX
LRX-PCB-SKEW
—
6
UI
Lane-to-lane skew at the
receiver that must be
tolerated. Note 14
Minimum RX drift tolerance
TRX-DRIFT
400
—
ps
15
Minim data tracking 3dB bandwidth
FTRK
0.2
—
MHz
16
Electrical idle entry detect time
TEI-ENTRY-DETECT
—60
ns
17
Electrical idle exit detect time
TEI-EXIT-DETECT
—30
ns
—
Bit Error Ratio
BER
—
10-12
—
18
NOTES:
1.
Specied at the package pins into a timing and voltage compliance
test setup. Note that signal levels at the pad will be lower than at the
pin.
2.
Single-ended voltages below that value that are simultaneously
detected on D+ and D- are interpreted as the Electrical Idle condition.
Worst- case margins are determined for the case with transmitter
using small voltage swing.
3.
Multiple lanes need to detect the El condition before the device can act
upon the El detection.
4..
Specic at the package pins into a timing and voltage compliance test
setup
5.
The single-pulse mask provides sufcient symbol energy for reliable
RX reception. Each symbol must comply with both the single-pulse
mask and the cumulative eyemask .
6.
The relative amplitude ratio limit between adjacent symbols prevents
excessive intersymbol interference in the RX. Each symbol must
comply with the peak amplitude ratio with regard to both the preceding
and subsequent symbols.
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