参数资料
型号: W3HG2128M72AEF665F2MBG
厂商: WHITE ELECTRONIC DESIGNS CORP
元件分类: DRAM
英文描述: 256M X 72 DDR DRAM MODULE, DMA240
封装: ROHS COMPLIANT, DIMM-240
文件页数: 6/18页
文件大小: 348K
代理商: W3HG2128M72AEF665F2MBG
14
W3HG2128M72AEF-Fx
June 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
14.
This number represents the lane-to-lane skew between TX and
RX pins and does not include the transmitter output skew from the
component driving the signal to the receiver. This is one component
of the end-to-end channel skew in the AMB specication.
15.
Measured from the reference clock edge to the center of the input
eye. This specication must be met across specied voltage and
temperature ranges for a single component. Drift rate of change is
signicantly below the tracking capability of the receiver.
16.
This bandwidth number assumes the specied minimum data
transition density. Maximum jitter at 0.2 MHz is 0.05 UI.
17.
The specied time includes the time required to forward the El entry
condition.
18.
BER per differential lane.
7.
This number does not include the effects of SSC or reference clock
jitter.
8.
This number includes setup and hold of the RX sampling op.
9.
Dened as the dual-dirac deterministic timing error.
10.
Allows for 15mV DC offset between transmit and receive devices.
11.
The received differential signal must satisfy both this ratio as well as
the absolute maximum AC peak-to-peak common mode specication.
For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-
to-peak common mode is the lesser of (200mV x 0.45=90mV) and
VRX-CM-AC-p-p.
12.
One of the components that contribute to the deterioration of the
return loss is the ESD structure which needs to be carefully designed.
13.
The termination small signal resistance; tolerance across voltages
from 100mV to 400mV shell not exceed +/- 5W with regard to the
average of the values measured at 100mV and at 400mV for that pin.
VRX-DIFFp-p = 2 x|VRX-D+ -VRX-D-|
(EQ 5)
VRX-CM = DC(avg) of (|VRX-D+ +VRX-D-|/(2)
(EQ 6)
VRX-CD-AC = ((Max|VRX-D+ +VRX-D-|)/(2) - ((Min |VRX-D++VRX-D-|)/2)
(EQ 7)
RRX-MATCH-DC = 2x ((|RRX-D+ -RRX-D-|)/(|RR-D++RRX-D-|))
(EQ 8)
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