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| 型号： | W6692ACF |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, ISDN CONTROLLER, PQFP100 |
| 封装： | QFP-100 |
| 文件页数： | 4/98页 |
| 文件大小： | 584K |
| 代理商： | W6692ACF |
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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-12 -
4. PIN DESCRIPTION
TABLE 4.1 W6692A PIN DESCRIPTIONS
Notation : The suffix "#" indicates an active LOW signal. In Intel or Motorola bus mode, all unspecified pins must be left
unconnected.
Pin
Name
Pin
Number
Type
Functions
PCI
Mode (Enabled when CLK toggles)
CLK
84
I
PCI Mode : PCI Clock. All other PCI signals, except RST#, INTA# are
sampled on the rising edge of CLK. According to PCI 2.1/2.2
specification, CLK is stable at least 100
s (Trst-clk) before deassertion
of RST#.
Intel Bus Mode : Must be pulled to HIGH.
Motorola Bus Mode : Must be pulled to LOW.
AD31-AD0
85,86,87,90,91,
92,93,94,97,98,
99,100,7,8,9,10,
23,24,25,30,33,
34,35,36,38,39,
40,41,44,45,46,
47
I/O
Address and Data are multiplexed on the same PCI pins. During the
address phase, AD31-0 contains a 32-bit physical address. During the
data phase, AD7-AD0 contains the least significant byte and AD31-
AD24 contain the most significant byte.
C/BE3#-C/BE0#
95,11,22,37
I
Bus command and Byte Enables.
During the address phase of a transaction, they define the bus
command.
During data phase, they are used as Byte Enables.
PAR
21
I/O
Parity is even parity across AD31-AD0 and C/BE3#-C/BE0#.
FRAME#
12
I
FRAME# is asserted to indicate a bus transaction is beginning.
TRDY#
14
O
Target Ready indicates W6692A is able to complete the current data
phase of the transaction.
IRDY#
13
I
Initiator Ready indicates the bus master
′s ability to complete the current
data phase of the transaction.
STOP#
18
O
Stop indicates W6692A is requesting the master to stop the current
transaction.
DEVSEL#
15
O
Device Select indicates W6692A has decoded itself as the target of the
current access.
IDSEL
96
I
Initialization Device Select is used as chip select during configuration
transactions.
PERR#
19
O
Parity Error is used for reporting of data parity errors.
RST#
81
I
PCI Reset. RST# may be asynchronous to CLK when asserted or
deasserted.
INTA#
80
O
Interrupt. This is level sensitive, active LOW and open drain output.
Intel Bus Mode (Enabled when CLK=HIGH)
CLK
84
I
This pin must be pulled to HIGH.
AD7-0
38,39,40,41,44,45
,46,47
I/O
Multiplexed address and data. During the address phase, AD7-0
contains a 8-bit physical address. During the data phase, AD7-AD0
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相关代理商/技术参数 |
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