Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-14 -
TESTP
61
I
Used to enable normal operation (1) or enter test mode (0).
PCI Power Management
PME
60
O
Power Management Event Signal. Level triggered, active HIGH. Drive
a transistor to PME# in PCI slot.
Peripheral Control
TOUT2
20
O
Timer 2 output. A square wave with 50 % duty cycle, 1~63 ms period
can be generated.
XINTIN0
52
I
A level change (either direction) will generate a maskable interrupt on
the PCI bus interrupt request pin INTA#.
XINTIN1
53
I
A level change (either direction) will generate a maskable interrupt on
the PCI bus interrupt request pin INTA#.
IO10-IO0
79,78,77,29,28,
27,26,4,3,2,1
I/O
When confiured as simple IO mode (PCTL:XMODE = 0), these pins
can read/write data from/to peripheral components. The pin directions
are selected via register. After hardware reset, the output drivers are
disabled.
XAD7-XAD0
29,28,27,26,
4,3,2,1
I/O
When configured as microprocessor mode (PCTL:XMODE = 1),
address and data are multiplexed on these pins.
XALE
77
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the Address Latch Enable output.
XRDB
78
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the read pulse.
XWRB
79
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the write pulse.
Power and Ground
VDDD
17,58,67,83
I
Digital Power Supply (5V
±5%).
VDDA
51
I
Analog Power Supply (5V
±5%).
VDDB
6,32,43,89
I
PCI Bus Power Supply (5V
±5%).
VSSD
16,59,68,82
I
Digital Ground.
VSSA
48
I
Analog Ground.
VSSB
5,31,42,88
I
PCI Bus Ground.