
Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-60 -
8.1.26 S/Q Channel Transmit Register
SQX
Read/Write
Address 64H/19H
Value after reset: 0FH
7
6
5
4
3
2
1
0
SCIE
Q1
Q2
Q3
Q4
SCIE
S Channel Change Interrupt Enable
This bit is used to enable/disable the generation of CIR:SCC status bit and interrupt.
0 : Status bit and interrupt are disabled.
1 : Status bit and interrupt are enabled.
Q1-4
Transmitted Q Bits
These are the transmitted Q channels in FA bit positions in frames 1, 6, 11 and 16. Q1 is in frame 1 and Q2 is in frame 6 etc.
A read to this register returns the previous written value.
8.1.27 Peripheral Control Register
PCTL
Read/Write
Address 68H/1AH
Value after reset: 00H
7
6
5
4
3
2
1
0
OE5
OE4
OE3
OE2
OE1
OE0
XMODE
PXC
OE5
Direction Control for IO10
Used when XMODE=0 only.
0: Pin IO10's output driver is disabled.
1: Pin IO10's output driver is enabled.
OE4
Direction Control for IO9-8
Used when XMODE=0 only.
0: Pin IO9-8's output drivers are disabled.
1: Pin IO9-8's output drivers are enabled.
OE3
Direction Control for IO7-6
Used when XMODE=0 only.
0: Pin IO7-6's output drivers are disabled.
1: Pin IO7-6's output drivers are enabled.
OE2
Direction Control for IO5-4
Used when XMODE=0 only.
0 : Pin IO5-4's output drivers are disabled.
1 : Pin IO5-4's output drivers are enabled.