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Data Sheet
W6692A PCI ISDN S/T-Controller
Publication Release Date:
Mar,2000
Revision 1.0
-17 -
7. FUNCTIONAL DESCRIPTIONS
7.1 Main Block Functions
The functional block diagram of W6692A is shown in Fig.6.1. The main function blocks are :
- Layer 1 function according to ITU-T I.430
- Serial Interface Bus (SIB)
- B channel switching
- GCI bus interface
- PCM port (x 2) and internal B channel switching
- D channel HDLC controller
- B channel HDLC controllers (x 2)
- PCI/microprocessor interface circuit
- Serial EEPROM interface for PCI Configuration purpose
- Peripheral control
The layer 1 function includes:
- S/T bus transmitter/receiver
- Timing recovery using Digital Phase Locked Loop (DPLL) circuit
- Layer 1 activation/deactivation, TE mode
- D channel access control
- Frame alignment
- Multi-frame synchronization
- Test functions
The serial interface bus performs the multiplexing/demultiplexing of D and 2B channels.
The B channel switching determines the connection between layer 1/GCI, layer 2 and PCM.
The GCI circuit is used to connect a U transceiver (slave mode) or other slave GCI device (master mode).
The PCM port provides two 64 kbps clear channels to connect to PCM codec chips.
The D channel HDLC controller performs the LAPD (Link Access Procedure on the D channel) protocol according to ITU-T
I.441/Q.921 recommendation.
There are two independent B channel HDLC controllers. They can be used to support HDLC-like protocols such as Internet PPP.
Two S/T B channels can also be programmed to 128Kbps mode with one HDLC controller to support IDSL or OCN (in Japan)
application.
The PCI interface circuit implements PCI specification revision 2.2 target mode function. In embedded application, a 8-bit
microprocessor interface is used to control the chip.