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参数资料
| 型号： | W942504CH-7 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件页数： | 11/45页 |
| 文件大小： | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
Publication Release Date: February 14, 2003
- 19 -
Revision A1
9. FUNCTIONAL DESCRIPTION
Power Up Sequence
1. Apply power and attempt to CKE at a low state (
≤ 0.2V), all other inputs may be undefined
1) Apply VDD before or at the same time as VDDQ.
2) Apply VDDQ before or at the same time as VTT and VREF.
2. Start Clock and maintain stable condition for 200
S(min).
3. After stable power and clock, apply NOP and take CKE high.
4. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
5. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(an additional 200 cycles(min) of clock are required for DLL Lock)
6. Issue precharge command for all banks of the device.
7. Issue two or more Auto Refresh commands.
8. Issue MRS-Initialize device operation.
(If device operation mode is set at sequence 5, sequence 8 can be skipped.)
Command Function
1. Bank Activate Command
( RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address)
The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row
addresses are latched on A0 to A12 when this command is issued and the cell data is read out of
the sense amplifiers. The maximum time that each bank can be held in the active state is specified
as tRAS (max). After this command is issued, Read or Write operation can be executed.
2. Bank Precharge Command
( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don’t
care)
The Bank Precharge command percharges the bank designated by BS. The precharged bank is
switched from the active state to the idle state.
3. Precharge All Command
( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don’t care, A10 = "H", A0 to A9, A11, A12 =
Don’t care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to
the idle state.
4. Write Command
( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11 = Column
Address)
The write command performs a Write operation to the bank designated by BS. The write data are
latched at both edges of DQS. The length of the write data (Burst Length) and column access
sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write
operation.
相关PDF资料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W942508BH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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