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参数资料
| 型号： | W942504CH-7 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件页数： | 12/45页 |
| 文件大小： | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
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Write Timing (Burst Length = 4)............................................................................................................. 29
Mode Register Set (MRS) Timing.......................................................................................................... 31
Extend Mode Register Set (EMRS) Timing ........................................................................................... 32
Auto Precharge Timing (Read Cycle, CL = 2) ....................................................................................... 33
Auto Precharge Timing (Write Cycle) .................................................................................................... 35
Read interrupted by Read (CL = 2, BL = 2, 4, 8) ................................................................................... 36
Burst Read Stop (BL = 8)....................................................................................................................... 36
Read Interrupted by Write & BST (BL = 8) ............................................................................................ 37
Read Interrupted by Precharge (BL = 8)................................................................................................ 37
Write Interrupted by Write (BL = 2, 4, 8) ................................................................................................ 38
Write Interrupted by Read (CL = 2, BL = 8) ........................................................................................... 38
Write Interrupted by Read (CL = 2. 5, BL = 4) ....................................................................................... 39
Write Interrupted by Precharge (BL = 8)................................................................................................ 39
2 Bank Interleave Read Operation (CL = 2, BL = 4).............................................................................. 40
4 Bank Interleave Read Operation (CL = 2, BL = 2).............................................................................. 41
4 Bank Interleave Read Operation (CL = 2, BL = 4).............................................................................. 41
Auto Refresh Cycle................................................................................................................................ 42
Active Power Down Mode Entry and Exit Timing .................................................................................. 42
Precharged Power Down Mode Entry and Exit Timing.......................................................................... 42
Self Refresh Entry and Exit Timing........................................................................................................ 43
11. PACKAGE DIMENSION.................................................................................................................. 44
TSOP 66l - 400 mil ................................................................................................................................ 44
12. VERSION HISTORY ....................................................................................................................... 45
相关PDF资料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W942508BH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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