参数资料
型号: W949D6CBHX5E
厂商: Winbond Electronics
文件页数: 49/60页
文件大小: 0K
描述: IC LPDDR SDRAM 512MBIT 60VFBGA
标准包装: 312
格式 - 存储器: RAM
存储器类型: 移动 LPDDR SDRAM
存储容量: 512M(32Mx16)
速度: 200MHz
接口: 并联
电源电压: 1.7 V ~ 1.95 V
工作温度: -25°C ~ 85°C
封装/外壳: 60-TFBGA
供应商设备封装: 60-VFBGA(8x9)
包装: 托盘
W949D6CB / W949D2CB
512Mb Mobile LPDDR
(X32)
PARAMETER
SYMBOL
TEST CONDITION
-5
-6
- 75
UNIT
Operating one
bank active-
precharge
current
IDD0
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are STABLE
40
38
35
mA
Precharge
power-down
standby current
Precharge
power-down
standby current
with clock stop
IDD2P
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK =
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
Low
power
Normal
power
Low
power
Normal
power
0.6
0.8
0.6
0.8
0.6
0.8
0.6
0.8
0.6
0.8
0.6
0.8
mA
mA
Precharge non
power-down
standby current
Precharge non
power-down
standby current
IDD2N
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus
inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are SWITCHING; data bus
10
3
10
3
10
3
mA
mA
with clock stop
inputs are STABLE
Active power-
down standby
current
IDD3P
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
3
3
3
mA
Active power-
down standby
current with
clock stop
Active non
power-down
standby current
IDD3PS
IDD3N
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
3
25
3
25
3
25
mA
mA
Active non
power-down
standby current
with clock stop
Operating burst
read current
Operating burst
write current
Auto-Refresh
Current
Deep Power-
Down current
IDD3NS
IDD4R
IDD4W
IDD5
IDD8(4)
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts;
IOUT = 0 mA; address inputs are SWITCHING; 50% data change each
burst transfer
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change
each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data bus inputs are
STABLE
Address and control inputs are STABLE; data bus inputs are STABLE
15
75
55
75
10
15
70
50
75
10
15
70
50
75
10
mA
mA
mA
mA
uA
Notes:
1.
2.
3.
4.
IDD specifications are tested after the device is properly initialized.
Input slew rate is 1V/ns.
Definitions for IDD:
LOW is defined as V IN ≤ 0.1 * V DDQ ;HIGH is defined as V IN ≥ 0.9 * V DDQ ; STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- Address and command: inputs changing between HIGH and LOW once per two clock cycles;
- Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
IDD8 are typical value at 25 ℃ .
Publication Release Date: Sep, 21, 2011
- 49 -
Revision A01-007
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