参数资料
型号: W9816G6IH-6
厂商: Winbond Electronics
文件页数: 8/42页
文件大小: 0K
描述: IC SDRAM 16MBIT 50TSOPII
标准包装: 117
格式 - 存储器: RAM
存储器类型: SDRAM
存储容量: 16M (1M x 16)
速度: 166MHz
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 50-TSOP(0.400",10.16mm 宽)
供应商设备封装: 50-TSOP II
包装: 托盘
W9816G6IH
7.5
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
7.6
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
7.7
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Publication Release Date: Mar. 22, 2010
-8-
Revision A02
相关PDF资料
PDF描述
AX1000-1FG896 IC FPGA AXCELERATOR 1M 896-FBGA
AX1000-FGG896I IC FPGA AXCELERATOR 1M 896-FBGA
AX1000-1FGG896 IC FPGA AXCELERATOR 1M 896-FBGA
W25Q16CVZPIG IC SPI FLASH 16MBIT 8WSON
W25Q80BWZPIG IC FLASH SPI 8MBIT 8WSON
相关代理商/技术参数
参数描述
W9816G6IH-6I 功能描述:IC SDRAM 16MBIT 50TSOPII RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,500 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?(单线) 电源电压:1.8 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP,8-MSOP(0.118",3.00mm 宽) 供应商设备封装:8-MSOP 包装:带卷 (TR)
W9816G6IH-7 制造商:WINBOND 制造商全称:Winbond 功能描述:512K 】 2 BANKS 】 16 BITS SDRAM
W9816G6IH-7I 制造商:WINBOND 制造商全称:Winbond 功能描述:512K 】 2 BANKS 】 16 BITS SDRAM
W982504AH-7 制造商:未知厂家 制造商全称:未知厂家 功能描述:x4 SDRAM
W982504AH-75 制造商:未知厂家 制造商全称:未知厂家 功能描述:x4 SDRAM