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参数资料
| 型号： | WED2DL32512V40BI |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 4 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 2/9页 |
| 文件大小： | 143K |
| 代理商： | WED2DL32512V40BI |
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL32512V
PIN DESCRIPTION
x36
Symbol
Type
Description
CLK
Input
Pulse
The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
4P
SA0
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of
4N
SA1
CLK.
2A, 2C, 2R, 2B
SA
3A, 3B, 3C, 3T
4T, 5A, 5B, 5C,
5T, 6A, 6B, 6C, 6R
5L
BWa
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup
5G
BWb
and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle.
3G
BWc
3L
BWd
BWa controls DQa’s and DQPa; BWb controls DQb’s and DQPb; BWc controls DQc’s and DQPc; BWd controls DQd’s and
DQPd.
4M
BWE
Input
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times
around the rising edge of CLK.
4K
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times around the clock’s rising edge.
4E
CE
Input
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP.
CE is sampled only when a new external address is loaded.
7T
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all
data in the memory array is retained. When active, all other inputs are ignored.
4F
OE
Input
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
4B
ADSC
Input
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external
address to be registered. A READ or WRITE is performed using the new address if CE is LOW. ADSC is also used to place
the chip into power-down state when CE is HIGH.
3R
MODE
Input
Mode: This input selects the burst sequence. A LOW on MODE selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is operating.
(a) 6K, 6L, 6M, 6N,
DQa
Input/
SRAM Data I/Os: Byte “a” is DQa’s; Byte “b” is DQb’s; Byte “c” is DQc’s;
7K, 7L, 7N, 7P
Output
Byte “d” is DQd’s. Input data must meet setup and hold times around rising edge of CLK.
(b) 6E, 6F, 6G, 6H,
DQb
7D, 7E, 7G, 7H
(c) 1D, 1E, 1G, 1H
DQc
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
DQd
2K, 2L, 2M, 2N
2J, 4C, 4J, 4R, 5R,
VDD
Supply
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
6J
1A, 1F, 1J, 1M 1U
VDDQ
Supply
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating
7A, 7F, 7J, 7M, 7U
Conditions for range.
3D, 3E, 3F, 3H, 3K,
VSS
Supply
Ground: GND.
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
2U
TMS
Input
Scan Test Mode Select
3U
TDI
Input
Scan Test Data In
4U
TDO
Output
Scan Test Data Out
5U
TCK
Input
Scan Test Clock
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