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参数资料
| 型号： | WED2DL32512V40BI |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 4 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 8/9页 |
| 文件大小： | 143K |
| 代理商： | WED2DL32512V40BI |
8
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL32512V
FIG. 4 WRITE TIMING DIAGRAM
NOTES:
1. D (A2) refers to output from address A2. D (A2+1) refers to output from the next internal burst address following A2.
2. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data content in for the time period
prior to the byte write enable inputs being sampled.
3. Full-width WRITE can be initiated by BWE, BWa, - BWd LOW. Timing is shown assuming that the device was not enabled before entering into its sequence.
OE does not cause Q to be driven until after the following clock rising edge.
tKHKL
tKLKH
tKHKH
t
KHG WX
t
tKHDX
tDVKH
D(A1)
D(A2)
D(A3)
D (A4)
D(A5)
tEVKH
tSCVKH
tKHSCX
tKHEX
tAVKH
tKHAX
A1
A2
A3
A4
A5
WVKH
KHWX
CLK
ADSC
DQ
ADDR
OE
WRITE
CE
DON’T CARE
UNDEFINED
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相关代理商/技术参数 |
参数描述 |
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| WED2DL32512V-B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SSRAM MCP |
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| WED2EG472512V5D2 | 制造商:WEDC 制造商全称:White Electronic Designs Corporation 功能描述:16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM |
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