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| 型号： | WJLXT971ALC.A4-857344 |
| 厂商： | CORTINA SYSTEMS INC |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封装： | 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64 |
| 文件页数： | 20/80页 |
| 文件大小： | 931K |
| 代理商： | WJLXT971ALC.A4-857344 |
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Page 27
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
5.4 Initialization
Force network link operation to:
— 100BASE-TX, Full-Duplex
— 100BASE-TX, Half-Duplex
— 10BASE-T, Full-Duplex
— 10BASE-T, Half-Duplex
Allow auto-negotiation/parallel-detection
On power-up or hardware reset, the LXT972A PHY reads the Hardware Control Interface
pins and sets the MDIO registers accordingly.
When the network link is forced to a specific configuration, the LXT972A PHY immediately
begins operating the network interface as commanded. When auto-negotiation is enabled,
the LXT972A PHY begins the auto-negotiation/parallel-detection operation.
5.4.2
Reduced-Power Modes
This section discusses the LXT972A PHY reduced-power modes.
5.4.2.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is
High, the following conditions are true:
The LXT972A PHY network port and clock are shut down.
All outputs are tristated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
5.4.2.2
Software Power Down
Software power-down control is provided by register bit 0.11 in the Control Register.
During soft power-down, the following conditions are true:
The network port is shut down.
The MDIO registers remain accessible.
5.4.3
Reset
The LXT972A PHY provides both hardware and software resets, each of which manage
differently the configuration control of auto-negotiation, speed, and duplex-mode
selection.
For a software reset, register bit 0.15 = 1. For register bit definitions used for software
reset, see Table 39, Control Register - Address 0, Hex 0, on page 64.
During a software reset, bit settings in Table 43, Auto-Negotiation Advertisement
Register - Address 4, Hex 4, on page 67 are not re-read from the LXT972A PHY
configuration pins. Instead, the bit settings revert to the values that were read in
during the last hardware reset. Therefore, any changes to pin values made since the
last hardware reset are not detected during a software reset.
During a software reset, registers are available for reading. To see when the LXT972A
PHY has completed reset, the reset bit can be polled (that is, register bit 0.15 = 0).
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