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参数资料
型号： WJLXT971ALC.A4-857344
厂商： CORTINA SYSTEMS INC
元件分类： 网络接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装： 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-64
文件页数： 64/80页
文件大小： 931K
代理商： WJLXT971ALC.A4-857344
Page 67
Cortina Systems LXT972A Single-Port 10/100 Mbps PHY Transceiver
LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
8.0 Register Definitions - IEEE
Base Registers
Table 43
Auto-Negotiation Advertisement Register - Address 4, Hex 4
Bit
Name
Description
Type 1
Default
4.15
Next Page
0 = Port has no ability to send multiple pages.
1 = Port has ability to send multiple pages.
R/W
0
4.14
Reserved
Ignore when read.
RO
0
4.13
Remote Fault
0 = No remote fault.
1 = Remote fault.
R/W
0
4.12
Reserved
Write as ‘0’. Ignore on Read.
R/W
0
4.11
Asymmetric Pause
Pause operation defined in IEEE 802.3 Standard,
Clause 40 and 27
R/W
0
4.10
Pause
0 = Pause operation disabled.
1 = Pause operation enabled for full-duplex link.
R/W
Note 2
4.9
100BASE-T4
0 = 100BASE-T4 capability is not available.
1 = 100BASE-T4 capability is available.
Note:
The LXT972A PHY does not support
100BASE-T4 but allows this bit to be set
to advertise in the auto-negotiation
sequence for 100BASE-T4 operation. An
external 100BASE-T4 PHY can be
switched in if this capability is desired.
R/W
0
4.8
100BASE-TX
full-duplex
(For LXT972A PHY)
0 = Port is not 100BASE-TX full-duplex capable.
1 = Port is 100BASE-TX full-duplex capable.
R/W
Note 3
4.7
100BASE-TX
(For LXT972A PHY)
0 = Port is not 100BASE-TX capable.
1 = Port is 100BASE-TX capable.
R/W
Note 3
4.6
10BASE-T
full-duplex
(ForLXT972A PHY)
0 = Port is not 10BASE-T full-duplex capable.
1 = Port is 10BASE-T full-duplex capable.
R/W
Note 3
4.5
10BASE-T
0 = Port is not 10BASE-T capable.
1 = Port is 10BASE-T capable.
R/W
Note 3
4.4:0
Selector Field,
S<4:0>
00001 =IEEE 802.3.
00010 =IEEE 802.9 ISLAN-16T.
00000 =Reserved for future auto-negotiation
development.
11111 = Reserved for future auto-negotiation
development.
Note:
Unspecified or reserved combinations
must not be transmitted.
R/W
00001
1. R/W = Read/Write
RO = Read Only
2. Default setting is determined by pin 33 at reset.
3. Some bits have their default values determined at reset by hardware configuration pins. For default details
for these bits, see Section 5.4.4, Hardware Configuration Settings.
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WJLXT971ALE.A4-857343 DATACOM, ETHERNET TRANSCEIVER, PQFP64
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