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参数资料
| 型号： | X1203S8T1 |
| 元件分类： | XO, clock |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | PLASTIC, SOIC-8 |
| 文件页数： | 13/19页 |
| 文件大小： | 155K |
| 代理商： | X1203S8T1 |
X1203
Characteristics subject to change without notice.
3 of 19
REV 1.2.0 2/13/01
www.xicor.com
course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a sepa-
rate latch to avoid time changes during the read opera-
tion. The clock continues to run. Alarms occurring
during a read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC reg-
isters. To avoid changing the current time by an incom-
plete write operation, the current time value is loaded
into a separate buffer at the falling edge of the clock on
the ACK bit before the RTC data input bytes, the clock
continues to run. The new serial input data replaces the
values in the buffer. This new RTC value is loaded back
into the RTC register by a stop bit at the end of a valid
write sequence. An invalid write operation aborts the
time update procedure and the contents of the buffer are
discarded. After a valid write operation the RTC will
reect the newly loaded data beginning with the rst
“one second” clock cycle after the stop bit. The RTC
continues to update the time while an RTC register write
is in progress and the RTC continues to run during any
nonvolatile write sequences. A single byte may be writ-
ten to the RTC without affecting the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area log-
ically separated from the array and are only accessible
following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR Access
The contents of the CCR can be modied by performing
a byte or a page write operation directly to any address
in the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to
the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes)
2. Alarm 1 (8 bytes)
3. Control (1 byte)
4. Real Time Clock (8 bytes)
5. Status (1 byte)
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The non volatile portion (or the counter
portion of the RTC) is updated only if RWEL is set and
after a valid write operation and stop bit. A sequential
read or page write operation provides access to the
contents of only one section of the CCR per operation.
Access to another section requires a new operation.
Continued reads or writes, once reaching the end of a
section, will wrap around to the start of the section. A
read or page write can begin at any address in the CCR.
Section 5) is a volatile register. It is not necessary to
set the RWEL bit prior to writing the status register.
Section 5) supports a single byte read or write only.
Continued reads or writes from this section terminates
the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time
being read. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24-hour time selection bit. The enable
bits specify which registers to use in the comparison
between the alarm and real time registers. For example:
– The user can set the X1203 to alarm every Wednesday
at 8:00AM by setting the EDWn, the EHRn and EMNn
enable bits to ‘1’ and setting the DWAn, HRAn and
MNAn Alarm registers to 8:00AM Wednesday.
– A daily alarm for 9:30PM results when the EHRn and
EMNn enable bits are set to ‘1’ and the HRAn and
MNAn registers set 9:30PM.
– Setting the EMOn bit in combination with other
enable bits and a specic alarm time, the user can
establish an alarm that triggers at the same time
once a year.
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| X1205S8I | 功能描述:IC RTC/CALENDAR 2-WIRE 8-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
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