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参数资料
| 型号： | X1203S8T1 |
| 元件分类： | XO, clock |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封装： | PLASTIC, SOIC-8 |
| 文件页数： | 4/19页 |
| 文件大小： | 155K |
| 代理商： | X1203S8T1 |
X1203
Characteristics subject to change without notice.
12 of 19
REV 1.2.0 2/13/01
www.xicor.com
DEVICE ADDRESSING
Following a start condition, the master must output a
slave address byte. The rst four bits of the slave
address byte specify access to the CCR. Slave bits
1101 access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to 111.
The last bit of the slave address byte denes the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 12.
After loading the entire slave address byte from the
SDA bus, the device compares the device identier and
device select bits with 1101111. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following the slave byte is a two byte CCR address.
The CCR address is either supplied by the master
device or obtained from an internal counter.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is, for a random read of the clock/
control registers, the slave byte must be 1101111x in
both places.
Figure 12. Slave Address, Word Address, and Data Bytes
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
00
0000
0
1
10
1
11
R/W
1
Device Identifier
0
High Order Word Address
Byte 1–X1203
Low Order Word Address
Byte 2–X1203
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