参数资料
型号: X40021V14I-CT1
厂商: Intersil
文件页数: 3/24页
文件大小: 0K
描述: IC VOLTAGE MONITOR DUAL 14-TSSOP
标准包装: 2,500
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 可调节/可选择
电压 - 阀值: 1.6V,2.9V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 带卷 (TR)
X40020, 40021
Low V CC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when V CC falls below the minimum V TRIP1 point.
RESET/RESET is active until V CC returns to proper
operating level and stabilizes. A second voltage moni-
tor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available. However, Intersil’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet specific system level requirements
or to fine-tune the threshold for applications requiring
higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
A battery switch circuit compares V CC with V BATT input
and connects V OUT to whichever is higher. This pro-
vides voltage to external SRAM or other circuits in the
event of main power failure. The X40020/21 can drive
PIN CONFIGURATION
X40020
14-Pin SOIC, TSSOP
50mA from V CC to 250μA from V BATT . The device only
switches to V BATT when V CC drops below the low V CC
voltage threshold and V BATT .
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device features an 2-wire interface and software
protocol allowing operation on a two-wire bus.
The device utilizes Intersil’s proprietary Direct Write ?
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X40021
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
V SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
BATT-ON
V OUT
V BATT
WP
SCL
SDA
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
V SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
BATT-ON
V OUT
V BATT
WP
SCL
SDA
PIN DESCRIPTION
Pin
1
2
3
4
5
6
Name
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET/
RESET
Function
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V TRIP2 and
goes HIGH when V2MON exceeds V TRIP2 . There is no power-up reset delay circuitry on this pin.
V2 Voltage Monitor Input. When the V2MON input is less than the V TRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V SS or V CC when
not used.
Early Low V CC Detect. This open drain output signal goes LOW when V CC < V TRIP1 .
When V CC > V TRIP1 , this pin is pulled high with the use of an external pull up resistor.
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the t PURST thereafter. It has an internal pull up
resistor.
RESET Output. (X40021) This open drain pin is an active LOW output which goes LOW whenever
V CC falls below V TRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t PURST ) on power-up. It will also stay active until manual reset is released and
for t PURST thereafter.
RESET Output. (X40020) This pin is an active HIGH open drain output which goes HIGH whenever
V CC falls below V TRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t PURST ) on power-up. It will also stay active until manual reset is released and
for t PURST thereafter.
3
FN8112.1
May 17, 2006
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