参数资料
| 型号： | X40021V14I-CT1 |
| 厂商： | Intersil |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MONITOR DUAL 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.6V，2.9V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
X40020, 40021
Resetting the V TRIPx Voltage
To reset a V TRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V TRIP1 and 0Bh for V TRIP2 , followed by 00h for the Data
Byte in order to reset V TRIPx . The STOP bit following a
valid write operation initiates the programming
Condition
V CC > V TRIP1
V CC > V TRIP1 &
V BATT = 0
0 ≤ V CC ≤ V TRIP1
and V CC < V BATT
Mode of Operation
Normal Operation
Normal Operation without battery
backup capability
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
sequence. Pin WDO must then be brought LOW to
complete the operation.
After being reset, the value of V TRIPx becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the registers.
System Battery Switch
As long as V CC exceeds the low voltage detect thresh-
old V TRIP , V OUT is connected to V CC through a 5 ? (typi-
cal) switch. When the V CC has fallen below V1 TRIP ,
then V CC is applied to V OUT if V CC is or equal to or
greater than V BATT - 0.03V. When V CC drops to less
than V BATT - 0.03V, then V OUT is connected to V BATT
through an 80 ? (typical) switch. V OUT typically supplies
the system static RAM voltage, so the switchover circuit
operates to protect the contents of the static RAM dur-
ing a power failure. Typically, when V CC has failed, the
SRAMs go into a lower power state and draw much less
current than in their active mode. When V CC returns,
V OUT switches back to V CC when V CC exceeds V BATT +
0.03V. There is a 60mV hysteresis around this battery
switch threshold to prevent oscillations between sup-
plies.
While V CC is connected to V OUT the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, and PUP0. The X40020 will not acknowl-
edge any data bytes written after the first byte is entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
7 6 5 4 3 2 1 0
during normal operation.
PUP1 WD1
WD0
0
0
RWEL WEL PUP0
Operation
The device is in normal operation with V CC as long as
V CC > V TRIP1 . It switches to the battery backup mode
when V CC goes away.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V TRIP Reset Circuit
V P
V TRIP1
Adj.
V TRIP2
Adj.
V2FAIL
RESET
4.7K
1
6
2
7
X40020
14
13
9
8
Adjust
Run
SCL
SDA
μC
7
FN8112.1
May 17, 2006
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