参数资料
| 型号： | X40239S16I-BT1 |
| 厂商： | Intersil |
| 文件页数： | 11/36页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MON TRPL EE 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.75V，2.95V，4.45V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
X40231, X40233, X40235, X40237, X40239
At both ends of each array and between each resistor
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
segment there is a CMOS switch connected between
the resistor array and the wiper (Rw x ) output. Within
each individual array, only one switch may be turned
on at any one time. These switches are controlled by
the Wiper Counter Register (WCR) (See Figure 6).
The WCR is a volatile register.
On power-up of the X4023x, wiper position data is au-
Issue Slave Address
Byte (Read or Write)
ACK
NO
Issue STOP
tomatically loaded into the WCR from its associated
Non Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
returned?
YES
DCP
R 0 (64 TAP)
R 1 (100 TAP)
Initial Values Before Recall
V H (TAP = 63)
V L (TAP = 0)
High Voltage Cycle
NO
R 2 (256 TAP)
V H (TAP = 255)
complete. Continue
command sequence?
YES
Continue normal
Read or Write
Issue STOP
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap posi-
tion to another.
command sequence
Hot Pluggability
PROCEED
Figure 7 shows a typical waveform that the X4023x
might experience in a Hot Pluggable situation. On
power-up, V CC applied to the X4023x may exhibit
Figure 5.
Acknowledge Polling Sequence
some amount of ringing, before it settles to the
required value.
The device is designed such that the wiper terminal
WIPER
COUNTER
N
R Hx
(R Wx ) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
V CC exceeds V TRIP1 for a time exceeding t PURST (the
Power-on Reset time, set in the CR Register - See
“CONTROL AND STATUS REGISTER” on page 18.).
REGISTER
(WCR)
NON
DECODER
2
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
Therefore, if t trans is defined as the time taken for V CC
to settle above V TRIP1 (Figure 7): then the desired
wiper terminal position is recalled by (a maximum)
time: t trans + t PURST . It should be noted that t trans is
determined by system hot plug conditions.
VOLATILE
MEMORY
(NVM)
Figure 6.
1
0
DCP Internal Structure
11
R Wx
DCP Operations
In total there are three operations that can be per-
formed on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
FN8115.0
April 11, 2005
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