参数资料
| 型号： | X40239S16I-BT1 |
| 厂商： | Intersil |
| 文件页数： | 9/36页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MON TRPL EE 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.75V，2.95V，4.45V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
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X40231, X40233, X40235, X40237, X40239
SCL
SDA
Start
Stop
Serial Start Condition
Figure 2.
Valid Start and Stop Conditions
The device will respond with an ACKNOWLEDGE
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition has been
met. See Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. The STOP condition is also used
to place the device into the Standby power mode after
a read sequence. A STOP condition can only be
issued after the transmitting device has released the
after recognition of a START condition if the correct
Device Identifier bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an ACKNOWLEDGE after the
receipt of each subsequent eight bit word.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master,
the device will continue to transmit data. The device
will terminate further data transmissions if an
ACKNOWLEDGE is not detected. The master must
then issue a STOP condition to place the device into a
known state.
bus. See Figure 2.
DEVICE INTERNAL ADDRESSING
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The trans-
mitting device, either master or slave, will release the
bus after transmitting eight bits. During the ninth clock
cycle, the receiver will pull the SDA line LOW to
ACKNOWLEDGE that it received the eight bits of data.
Refer to Figure 3
Addressing Protocol Overview
The user addressable internal components of the
X4023x can be split up into three main parts:
—One or Two Digitally Controlled Potentiometers
(DCPs)
—EEPROM array
—Control and Status (CR) Register
SCL from
Master
1
8
9
Data Output from
Transmitter
Data Output
from Receiver
Start
Figure 3.
9
Acknowledge
Acknowledge Response From Receiver
FN8115.0
April 11, 2005
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