参数资料
| 型号： | X40239S16I-BT1 |
| 厂商： | Intersil |
| 文件页数： | 16/36页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MON TRPL EE 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.75V，2.95V，4.45V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
X40231, X40233, X40235, X40237, X40239
7 bytes
5
5 bytes
address
= 6 10
address
11 10
address
15 10
address pointer
ends here
Addr = 7 10
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
1 0 1 0 0 0 0 1
A
C
K
Data
S
t
o
p
Figure 14. Current EEPROM Address Read Sequence
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an ACKNOWLEDGE
and then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an ACKNOWLEDGE during the ninth
clock and then issues a STOP condition (See Figure
14 for the address, ACKNOWLEDGE, and data trans-
fer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a STOP condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access
to a DCP or the CR Register (i.e.: an operation using
16
the Device Type Identifier 1010111 or 1010010).
Immediately after an operation to a DCP or CR Regis-
ter is performed, only a “Random EEPROM Read” is
available. Immediately following a “Random EEPROM
Read” , a “Current EEPROM Address Read” or
“Sequential EEPROM Read” is once again available
(assuming that no access to a DCP or CR Register
occur in the interim).
Random EEPROM Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the START condition and the Slave
Address Byte, receives an ACKNOWLEDGE, then
issues an Address Byte. This “dummy” Write operation
sets the address pointer to the address from which to
begin the random EEPROM read operation.
After the X4023x acknowledges the receipt of the
Address Byte, the master immediately issues another
START condition and the Slave Address Byte with the
R/W bit set to one. This is followed by an ACKNOWL-
EDGE from the X4023x and then by the eight bit word.
FN8115.0
April 11, 2005
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