参数资料
| 型号： | X40239S16I-BT1 |
| 厂商： | Intersil |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC VOLTAGE MON TRPL EE 16-SOIC |
| 标准包装： | 1,000 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 1.75V，2.95V，4.45V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
X40231, X40233, X40235, X40237, X40239
X40237 PIN ASSIGNMENT
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
R H2
R W2
V3MON
V3FAIL
MR
WP
SCL
SDA
VSS
NC
R H0
R W0
V2MON
V2FAIL
RESET
V CC
Function
Connection to end of resistor array for (the 256 Tap) DCP2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP2.
V3MON Voltage Monitor Input.
V3MON is the input to a non-inverting voltage comparator circuit. When the V3MON input is higher than
the V TRIP3 threshold voltage, V3FAIL makes a transition to a HIGH level. Connect V3MON to V SS when
not used.
V3MON RESET Output.
This open drain output makes a transition to a HIGH level when V3MON is greater than V TRIP3 and goes
LOW when V3MON is less than VTRIP3. There is no delay circuitry on this pin. The V3FAIL pin requires
the use of an external “pull-up” resistor.
Manual Reset. MR is a TTL level compatible input.
Pulling the MR pin active (HIGH) initiates a reset cycle to the RESET pin (V CC RESET Output pin).
RESET will remain HIGH for time t PURST after MR has returned to it’s normally LOW state. The reset
time can be selected using bits PUP1 and PUP0 in the CR Register. The MR pin requires the use of an
external “pull-down” resistor.
Write Protect Control Pin.
WP pin is a TTL level compatible input. When held HIGH, Write Protection is enabled. In the enabled
state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and
the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile
or nonvolatile) operations can be performed in the device (including the wiper position of any of the
integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor,
thus if left floating the write protection feature is disabled.
Serial Clock.
This is a TTL level compatible input pin used to control the serial bus timing for data input and output.
Serial Data.
SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA
pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
No Connect
Connection to end of resistor array for (the 64 Tap) DCP0.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP0.
V2MON Voltage Monitor Input.
V2MON is the input to a non-inverting voltage comparator circuit. When the V2MON input is greater than
the V TRIP2 threshold voltage, V2FAIL makes a transition to a HIGH level. Connect V2MON to V SS when
not used.
V2MON RESET Output.
This open drain output makes a transition to a HIGH level when V2MON is greater than V TRIP2 , and goes
LOW when V2MON is less than V TRIP2 . There is no power-uppower-up reset delay circuitry on this pin.
The V2FAIL pin requires the use of an external “pull-up” resistor.
V CC RESET Output.
This is an active HIGH, open drain output which becomes active whenever V CC falls below V TRIP1 .
RESET becomes active on power-up and remains active for a time t PURST after the power supply
stabilizes (t PURST can be changed by varying the PUP0 and PUP1 bits of the internal control register).
The RESET pin requires the use of an external “pull-up” resistor. The RESET pin can be forced active
(HIGH) using the manual reset (MR) input pin.
Supply Voltage.
6
FN8115.0
April 11, 2005
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