参数资料
| 型号： | X40626V14T1 |
| 厂商： | Intersil |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU DUAL 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.93V，4.38V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
X40626
Figure 15. X40626 Addressing
Device Identifier
Device Select
1
0
1
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
A15
A14
A13
A12
A11
A10
A9
A8
Word Address Byte 1
Low Order Word Address
A7
A6
A5
A4
A3
A2
A1
A0
Word Address Byte 0
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is in the input mode.
– RESET Signal is active for t PURST .
– Communication to the device is inhibited while
RESET is active and any in-progress communica-
tion is terminated.
– Block Lock bits can protect sections of the memory
array from write operations.
Symbol Table
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
14
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
FN8119.0
March 28, 2005
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