参数资料
| 型号： | X40626V14T1 |
| 厂商： | Intersil |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU DUAL 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.93V，4.38V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
X40626
CAPACITANCE (T A = 25°C, f = 1.0 MHz, V CC = 5V)
Symbol
Parameter
Max.
Units
Test Conditions
C OUT
(4)
Output Capacitance (SDA, RESET, V2FAIL)
8
pF
V OUT = 0V
C IN
(4)
Input Capacitance (SCL, WP, S0, S1)
6
pF
V IN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
SDA
RESET
5V
1533 ?
30pF
V2MON
1.53k ?
V2FAIL
30pF
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1V CC to 0.9V CC
10ns
0.5V CC
Standard Output Load
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
f SCL
t IN
t AA
t BUF
t LOW
t HIGH
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t DH
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
Max.
400
0.9
Units
kHz
ns
μ s
μ s
μ s
μ s
μ s
μ s
ns
μ s
μ s
ns
t R
t F
SDA and SCL Rise Time
SDA and SCL Fall Time
20 +
20 +
0.1Cb (2)
0.1Cb (2)
300
300
ns
ns
t SU:WP
t HD:WP
Cb
WP Setup Time
WP Hold Time
Capacitive load for each bus line
0.6
0
400
μ s
μ s
pF
Notes: (1) Typical values are for T A = 25°C and V CC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
16
FN8119.0
March 28, 2005
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