参数资料
| 型号： | X40626V14T1 |
| 厂商： | Intersil |
| 文件页数： | 4/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU DUAL 14-TSSOP |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 2 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.93V，4.38V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
X40626
Resetting the V TRIP Voltage
This procedure is used to set the V TRIP to a “native”
voltage level. For example, if the current V TRIP is 4.4V
and the new V TRIP must be 4.0V, then the V TRIP must
be reset. When V TRIP is reset, the new V TRIP is some-
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
To reset the new V TRIP voltage start by setting the
WEL bit in the control register, apply the desired V TRIP
threshold voltage to the V CC pin and the programming
voltage, V P , to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit of a valid write operation
initiates the V TRIP programming sequence. Bring WP
LOW to complete the operation.
Figure 2. Reset V TRIP Level Sequence (V CC /V 2MON > 3V, WP = 12-15V, WEL bit set)
WP
V P = 12-15V
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0H
00H
xxH*
00H
*for V TRIP2 address is 0FH
for V TRIP address is 03H
Figure 3. Sample V TRIP Reset Circuit
V P
V TRIP
Adj.
RESET
4.7K
1
2
3
4
5
6
7
X40626
14
13
12
9
8
Adjust
Run
SCL
SDA
μC
4
FN8119.0
March 28, 2005
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