参数资料
| 型号： | X4325V8I-2.7 |
| 厂商： | Intersil |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 32K EE 8-TSSOP |
| 标准包装： | 200 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 复位： | 高有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
X4323, X4325
CAPACITANCE (T A = 25°C, f = 1.0 MHz, V CC = 5V)
Symbol
Parameter
Max.
Units
Test Conditions
C OUT
(4)
Output Capacitance (SDA, RST/RST)
8
pF
V OUT = 0V
C IN (4)
Input Capacitance (SCL, WP)
6
pF
V IN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
5V
Input pulse levels
Input rise and fall times
0.1V CC to 0.9V CC
10ns
SDA
1533 ?
For V OL = 0.4V
and I OL = 3 mA
Input and output timing levels
Output load
0.5V CC
Standard output load
or
RESET
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
f SCL
t IN
t AA
t BUF
t LOW
t HIGH
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t DH
t R
t F
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
20 +.1Cb
Max.
400
0.9
300
300
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
t SU:WP
t HD:WP
Cb
WP Setup Time
WP Hold Time
Capacitive load for each bus line
0.6
0
400
μs
μs
pF
Notes: (1) Typical values are for T A = 25°C and V CC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
17
FN8122.1
May 25, 2006
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