参数资料
| 型号： | X4325V8I-2.7 |
| 厂商： | Intersil |
| 文件页数： | 5/22页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 32K EE 8-TSSOP |
| 标准包装： | 200 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 复位： | 高有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 2.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
X4323, X4325
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4323, X4325 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V CC exceeds the device V TRIP threshold value
for 200ms (nominal) the circuit releases
RESET/RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4323, X4325 monitors the V CC
level and asserts RESET/RESET if supply voltage
falls below a preset minimum V TRIP . The
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
V CC returns and exceeds V TRIP for 200ms.
WATCHDOG TIMER
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V CC THRESHOLD RESET PROCEDURE
The X4323, X4325 is shipped with a standard V CC
threshold (V TRIP ) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard V TRIP is not
exactly right, or if higher precision is needed in the
V TRIP value, the X4323, X4325 threshold may be
adjusted. The procedure is described in the following
section, and uses the application of a nonvolatile con-
trol signal.
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
Figure 1. Set V TRIP Level Sequence (V CC = desired V TRIP values WEL bit set)
WP
V P = 12-15V
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
5
00h
01h
00h
FN8122.1
May 25, 2006
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