参数资料
| 型号： | X9252YV24IZ-2.7 |
| 厂商： | Intersil |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL QUAD 24-TSSOP |
| 标准包装： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 电阻（欧姆）： | 2.8k |
| 电路数： | 4 |
| 温度系数： | 标准值 ±300 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C（芯片选择，设备位址，增/减） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1237 (CN2011-ZH PDF) |
2
FN8167.2
November 14, 2005
Functional Diagram
Ordering Information
PART NUMBER
PART MARKING
RTOTAL (k)
TEMP RANGE (°C)
PACKAGE
X9252YS24I-2.7
2.8
-40 to 85
24 Ld SOIC (300 mil)
X9252YS24IZ-2.7 (Note)
-40 to 85
24 Ld SOIC (300 mil) (Pb-Free)
X9252YV24I-2.7
X9252YV G
-40 to 85
24 Ld TSSOP (4.4mm)
X9252YV24IZ-2.7 (Note)
X9252YV Z G
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
X9252WS24I-2.7
X9252WS G
10
-40 to 85
24 Ld SOIC (300 mil)
X9252WS24IZ-2.7 (Note)
X9252WS Z G
-40 to 85
24 Ld SOIC (300 mil) (Pb-Free)
X9252WV24I-2.7
X9252WV G
-40 to 85
24 Ld TSSOP (4.4mm)
X9252WV24IZ-2.7 (Note)
X9252WV Z G
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
X9252US24I-2.7
X9252US G
50
-40 to 85
24 Ld SOIC (300 mil)
X9252US24IZ-2.7 (Note)
X9252US Z G
-40 to 85
24 Ld SOIC (300 mil) (Pb-Free)
X9252UV24I-2.7
X9252UV G
-40 to 85
24 Ld TSSOP (4.4mm)
X9252UV24IZ-2.7 (Note)
X9252UV Z G
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
X9252TS24I-2.7
X9252TS G
100
-40 to 85
24 Ld SOIC (300 mil)
X9252TS24IZ-2.7 (Note)
X9252TS Z G
-40 to 85
24 Ld SOIC (300 mil) (Pb-Free)
X9252TV24I-2.7
X9252TV G
-40 to 85
24 Ld TSSOP (4.4mm)
X9252TV24IZ-2.7 (Note)
X9252TV Z G
-40 to 85
24 Ld TSSOP (4.4mm) (Pb-free)
Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
POWER UP,
INTERFACE
CONTROL
AND
VCC
VSS
2-Wire
RH0
RL0
DCP0
RW0
A1
SDA
SCL
CS
U/D
A2
DS0
DS1
WP
WCR0
DR00
DR01
DR02
DR03
RH1
RL1
DCP1
RW1
WCR1
DR10
DR11
DR12
DR13
RH2
RL2
DCP2
RW2
WCR2
DR20
DR21
DR22
DR23
RH3
RL3
DCP3
RW3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
Up-Down
Interface
STATUS
Pin Descriptions
SOIC/TSSOP PIN
SYMBOL
BRIEF DESCRIPTION
1
DS0
DCP select for Up/Down interface.
2
A0
Device address for 2-wire bus.
3
RW3
Wiper terminal of DCP3.
4
RH3
High terminal of DCP3.
X9252
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相关代理商/技术参数 |
参数描述 |
|---|---|
| X9258 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Low Noise/Low Power/2-Wire Bus/256 Taps |
| X9258)06 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers |
| X9258_11 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers(XDCP?) |
| X9258_13 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Low Noise/Low Power/2-Wire Bus/256 Taps |
| X9258TB24 | 制造商:XICOR 制造商全称:Xicor Inc. 功能描述:Quad Digital Controlled Potentiometers (XDCP) |
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