参数资料
| 型号： | XA3S1200E-4FGG400I |
| 厂商： | Xilinx Inc |
| 文件页数： | 17/37页 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3E 1200K 400-FBG |
| 标准包装： | 60 |
| 系列： | Spartan®-3E XA |
| LAB/CLB数： | 8672 |
| 逻辑元件/单元数： | 19512 |
| RAM 位总计： | 516096 |
| 输入/输出数： | 304 |
| 门数： | 1200000 |
| 电源电压： | 1.14 V ~ 1.26 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 400-BGA |
| 供应商设备封装： | 400-FBGA（21x21） |
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DS635 (v2.0) September 9, 2009
Product Specification
24
R
Digital Clock Manager Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital Fre-
quency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM applica-
tions. All such applications inevitably use the CLKIN and the
CLKFB inputs connected to either the CLK0 or the CLK2X
feedback, respectively. Thus, specifications in the DLL
only employs the DLL component. When the DFS and/or
the PS components are used together with the DLL, then
the specifications listed in the DFS and PS tables (Table 28
through Table 31) supersede any corresponding ones in the
DLL tables. DLL specifications that do not change with the
addition of DFS or PS functions are presented in Table 26
and Table 27.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a histo-
gram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock peri-
ods sampled. In a histogram of cycle-cycle jitter, the mean
value is zero.
Spread Spectrum
DCMs accept typical spread spectrum clocks as long as
they meet the input requirements. The DLL will track the fre-
quency changes created by the spread spectrum clock to
drive the global clocks to the FPGA logic. See XAPP469,
Spread-Spectrum Clocking Reception for Displays
for details.
Clock Timing
TBPWH
High pulse width of the CLK signal
1.59
-ns
TBPWL
Low pulse width of the CLK signal
1.59
-ns
Clock Frequency
FBRAM
Block RAM clock frequency. RAM read output value written back
into RAM, for shift registers and circular buffers. Write-only or
read-only performance is faster.
0230
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 6.
Table 25: Block RAM Timing (Continued)
Symbol
Description
-4 Speed Grade
Units
Min
Max
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