参数资料
| 型号： | XC2S100E-6FT256C |
| 厂商： | Xilinx Inc |
| 文件页数： | 59/108页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V 600 CLB'S 256-FBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 90 |
| 系列： | Spartan®-IIE |
| LAB/CLB数： | 600 |
| 逻辑元件/单元数： | 2700 |
| RAM 位总计： | 40960 |
| 输入/输出数： | 182 |
| 门数： | 100000 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-FTBGA |
| 其它名称： | 122-1208 |
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54
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
D0/DIN, D1, D2, D3,
D4, D5, D6, D7
No
Input or Output
In Slave Parallel mode, D0-D7 are configuration data input pins.
During readback, D0-D7 are output pins. These pins become
user I/Os after configuration unless the Slave Parallel port is
retained.
In serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
WRITE
No
Input
In Slave Parallel mode, the active-low Write Enable signal. This
pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
CS
No
Input
In Slave Parallel mode, the active-low Chip Select signal. This pin
becomes a user I/O after configuration unless the Slave Parallel
port is retained.
TDI, TDO, TMS, TCK
Yes
Mixed
Boundary Scan Test Access Port pins (IEEE 1149.1).
VCCINT
Yes
Input
1.8V power supply pins for the internal core logic.
VCCO
Yes
Input
Power supply pins for output drivers (1.5V, 1.8V, 2.5V, or 3.3V
subject to banking rules in the Functional Description module.
VREF
No
Input
Input threshold reference voltage pins. Become user I/Os when
an external threshold voltage is not needed (subject to banking
rules in the Functional Description module.
GND
Yes
Input
Ground. All must be connected.
IRDY, TRDY
No
See PCI core
documentation
These signals can only be accessed when using Xilinx PCI cores.
If the cores are not used, these pins are available as user I/Os.
L#[P/N]
(e.g., L0P)
No
Bidirectional
Differential I/O with synchronous output. P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
L#[P/N]_Y
(e.g., L0P_Y)
No
Bidirectional
Differential I/O with asynchronous or synchronous output
(asynchronous output not compatible for all densities in a
package). P = positive, N = negative. The number (#) is used to
associate the two pins of a differential pair. Becomes a general
user I/O when not needed for differential signals.
L#[P/N]_YY
(e.g., L0P_YY)
No
Bidirectional
Differential I/O with asynchronous or synchronous output
(compatible for all densities in a package). P = positive, N =
negative. The number (#) is used to associate the two pins of a
differential pair. Becomes a general user I/O when not needed for
differential signals.
I/O
No
Bidirectional
These pins can be configured to be input and/or output after
configuration is completed. Unused I/Os are disabled with a weak
pull-down resistor. After power-on and before configuration is
completed, these pins are either pulled up or left floating
according to the Mode pin values. See the DC and Switching
Characteristics module for power-on characteristics.
Pin Definitions (Continued)
Pad Name
Dedicated
Pin
Direction
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S100E6FT256I | 制造商:Xilinx 功能描述: |
| XC2S100E-6FT256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6FTG256C | 功能描述:IC SPARTAN-IIE FPGA 100K 256FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
| XC2S100E-6FTG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6PQ208C | 功能描述:IC FPGA 1.8V 600 CLB'S 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 标准包装:40 系列:Spartan® 6 LX LAB/CLB数:3411 逻辑元件/单元数:43661 RAM 位总计:2138112 输入/输出数:358 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:676-BGA 供应商设备封装:676-FBGA（27x27） |
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