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参数资料
型号： XC2S200E-6PQG208C
厂商： Xilinx Inc
文件页数： 38/108页
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 200K 208PQFP
标准包装： 24
系列： Spartan®-IIE
LAB/CLB数： 1176
逻辑元件/单元数： 5292
RAM 位总计： 57344
输入/输出数： 146
门数： 200000
电源电压： 1.71 V ~ 1.89 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 208-BFQFP
供应商设备封装： 208-PQFP（28x28）
其它名称： 122-1324
DS077-3 (v3.0) August 9, 2013
www.xilinx.com
35
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
Symbol
Description
Speed Grade
Units
All
-7
-6
Min
Max
TICKOFDLL
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
1.0
3.1
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3.
DLL output jitter is already included in the timing calculation.
4.
For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
Symbol
Description
Device
Speed Grade
Units
All
-7
-6
Min
Max
TICKOF
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E
1.5
4.4
4.6
ns
XC2S100E
1.5
4.4
4.6
ns
XC2S150E
1.5
4.5
4.7
ns
XC2S200E
1.5
4.5
4.7
ns
XC2S300E
1.5
4.5
4.7
ns
XC2S400E
1.5
4.6
4.8
ns
XC2S600E
1.6
4.7
4.9
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3.
For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
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