参数资料
型号: XC2S200E-6PQG208C
厂商: Xilinx Inc
文件页数: 58/108页
文件大小: 0K
描述: IC SPARTAN-IIE FPGA 200K 208PQFP
标准包装: 24
系列: Spartan®-IIE
LAB/CLB数: 1176
逻辑元件/单元数: 5292
RAM 位总计: 57344
输入/输出数: 146
门数: 200000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
其它名称: 122-1324
DS077-4 (v3.0) August 9, 2013
53
Product Specification
2001–-2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Introduction
This section describes how the various pins on a
Spartan-IIE FPGA connect within the supported
component packages, and provides device-specific thermal
characteristics. Spartan-IIE FPGAs are available in both
standard and Pb-free, RoHS versions of each package, with
the Pb-free version adding a “G” to the middle of the
package code. Except for the thermal characteristics, all
information for the standard package applies equally to the
Pb-free package.
Pin Types
Most pins on a Spartan-IIE FPGA are general-purpose,
user-defined I/O pins. There are, however, different
functional types of pins on Spartan-IIE FPGA packages, as
outlined below.
Spartan-IIE FPGA Family:
Pinout Tables
DS077-4 (v3.0) August 9, 2013
0
Product Specification
R
Pin Definitions
Pad Name
Dedicated
Pin
Direction
Description
GCK0, GCK1, GCK2,
GCK3
No
Input
Clock input pins that connect to Global Clock buffers or DLL
inputs. These pins become user inputs when not needed for
clocks.
DLL
No
Input
Clock input pins that connect to DLL input or feedback clocks.
Differential clock input (N input of pair) when paired with adjacent
GCK input. Becomes a user I/O when not needed for clocks.
M0, M1, M2
Yes
Input
Mode pins used to specify the configuration mode.
CCLK
Yes
Input or Output
The configuration Clock I/O pin. It is an input for Slave Parallel
and Slave Serial modes, and output in Master Serial mode. After
configuration, it is an input only with Don’t Care logic levels.
PROGRAM
Yes
Input
Initiates a configuration sequence when asserted Low.
DONE
Yes
Bidirectional
Indicates that configuration loading is complete, and that the
start-up sequence is in progress. The output may be open drain.
INIT
No
Bidirectional
(Open-drain)
When Low, indicates that the configuration memory is being
cleared. Goes High to indicate the end of initialization. Goes back
Low to indicate a CRC error. This pin becomes a user I/O after
configuration.
DOUT/BUSY
No
Output
In Slave Parallel mode, BUSY controls the rate at which
configuration data can be loaded. It is not needed below 50 MHz.
This pin becomes a user I/O after configuration unless the Slave
Parallel port is retained.
In serial modes, DOUT provides configuration data to
downstream devices in a daisy-chain. This pin becomes a user
I/O after configuration.
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