Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
98
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are
available as full-featured user-I/O pins.
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to
disable the pull-up resistors. The HSWAP control must
remain at a constant logic level throughout FPGA
configuration. After configuration, when the FPGA’s DONE
output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
Voltage Compatibility
Most Slave Serial interface signals are within the
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V VCCAUX supply. See XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional
information.
Daisy-Chaining
If the application requires multiple FPGAs with different
configurations, then configure the FPGAs using a daisy
chain, as shown in
Figure 64. Use Slave Serial mode
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
X-Ref Target - Figure 63
Figure 63: Slave Serial Configuration
+2.5V
TDI
TDO
TMS
TCK
VCCINT
VCCAUX
+2.5V
VCCO_2
INIT_B
PROG_B
DONE
GND
+1.2V
HSWAP
VCCO_0
P
VCCO_0
4.
7
k
Spartan-3E
FPGA
+2.5V
JTAG
PROG_B
Recommend
open-drain
driver
TDI
TMS
TCK
TDO
M2
M1
‘1’
M0
‘1’
DOUT
33
0
DIN
CCLK
V
Slave
Serial
Mode
4.
7k
V
CLOCK
SERIAL_OUT
PROG_B
INIT_B
DONE
V
VCC
GND
Configuration
Memory
Source
Internal memory
Disk drive
Over network
Over RF link
Intelligent
Download Host
Microcontroller
Processor
Tester
Computer
DS312-2_54_082009
P
V