Spartan-3 FPGA Family: Introduction and Ordering Information
DS099 (v3.1) June 27, 2013
Product Specification
4
power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master
Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit-wide SelectMAP port.
The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which
includes the XCF00S PROMs for serial configuration and the higher density XCF00P PROMs for parallel or serial
configuration.
I/O Capabilities
The SelectIO feature of Spartan-3 devices supports eighteen single-ended standards and eight differential standards as
listed in
Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal
reflections.
Table 2: Signal Standards Supported by the Spartan-3 Family
Standard
Category
Description
VCCO (V)
Class
Symbol
(IOSTANDARD)
DCI
Option
Single-Ended
GTL
Gunning Transceiver Logic
N/A
Terminated
GTL
Yes
Plus
GTLP
Yes
HSTL
High-Speed Transceiver Logic
1.5
I
HSTL_I
Yes
III
HSTL_III
Yes
1.8
I
HSTL_I_18
Yes
II
HSTL_II_18
Yes
III
HSTL_III_18
Yes
LVCMOS
Low-Voltage CMOS
1.2
N/A
LVCMOS12
No
1.5
N/A
LVCMOS15
Yes
1.8
N/A
LVCMOS18
Yes
2.5
N/A
LVCMOS25
Yes
3.3
N/A
LVCMOS33
Yes
LVTTL
Low-Voltage Transistor-Transistor Logic
3.3
N/A
LVTTL
No
PCI
Peripheral Component Interconnect
3.0
PCI33_3
No
SSTL
Stub Series Terminated Logic
1.8
N/A (
±6.7 mA)
SSTL18_I
Yes
N/A (
±13.4 mA)
SSTL18_II
No
2.5
I
SSTL2_I
Yes
II
SSTL2_II
Yes
Differential
LDT
(ULVDS)
Lightning Data Transport (HyperTransport)
Logic
2.5
N/A
LDT_25
No
LVDS
Low-Voltage Differential Signaling
Standard
LVDS_25
Yes
Bus
BLVDS_25
No
Extended Mode
LVDSEXT_25
Yes
LVPECL
Low-Voltage Positive Emitter-Coupled Logic
2.5
N/A
LVPECL_25
No
RSDS
Reduced-Swing Differential Signaling
2.5
N/A
RSDS_25
No
HSTL
Differential High-Speed Transceiver Logic
1.8
II
DIFF_HSTL_II_18
Yes
SSTL
Differential Stub Series Terminated Logic
2.5
II
DIFF_SSTL2_II
Yes
Notes:
1.
66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.