Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013
Product Specification
67
X-Ref Target - Figure 33
Figure 33: Differential Output Voltages
Table 38: DC Characteristics of User I/Os Using Differential Signal Standards
Signal Standard
Revision
VOD
VOCM
VOH
VOL
Min (mV) Typ (mV)
Max (mV)
Min (V)
Typ (V)
Max (V)
Min (V)
Max (V)
LDT_25 (ULVDS_25)
All
600
670
0.495
0.600
0.715
0.71
0.50
LVDS_25
All
100
–
600
0.80
–
1.6
0.85
1.55
‘E’
200
–
500
1.0
–
1.5
1.10
1.40
All
250
350
450
–
1.20
–
LVDSEXT_25
All
100
–
600
0.80
–
1.6
0.85
1.55
‘E’
300
–
700
1.0
–
1.5
1.15
1.35
All
–
-
–
-
1.35
1.005
All
100
–
600
0.80
–
1.6
0.85
1.55
‘E’
200
–
500
1.0
–
1.5
1.10
1.40
DIFF_HSTL_II_18
All
–
VCCO – 0.40
0.40
DIFF_SSTL2_II
All
–
VTT + 0.80
VTT – 0.80
Notes:
1.
The numbers in this table are based on the conditions set forth in
Table 32 and
Table 37.2.
Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the
differential signal pair.
3.
Mask revision E devices have tighter output ranges but can be used in any design that was in a previous revision. See
Mask and Fab4.
This value must be compatible with the receiver to which the FPGA’s output pair is connected.
5.
Each LVPECL_25 or BLVDS_25 output-pair requires three external resistors for proper output operation as shown in
Figure 34. Each
LVPECL_25 or BLVDS_25 input-pair uses a 100W termination resistor at the receiver.
6.
Only one of the differential standards RSDS_25, LDT_25, LVDS_25, and LVDSEXT_25 may be used for outputs within a bank.
Each differential standard input-pair requires an external 100
Ω termination resistor.
X-Ref Target - Figure 34
Figure 34: External Termination Required for LVPECL and BLVDS Output and Input
DS099-3_02_091710
V
OUTN
V
OUTP
GND level
50%
V
OCM
V
OCM
V
OD
V
OL
V
OH
V
OUTP
Internal
Logic
V
OUTN
N
P
= Output common mode voltage =
2
V
OUTP
+ V
OUTN
V
OD = Output differential voltage =
V
OH = Output voltage indicating a High logic level
V
OL
= Output voltage indicating a Low logic level
V
OUTP
- V
OUTN
Differential
I/O Pair Pins
ds099-3_08_112105
240
Ω
70
Ω
70
Ω
100
Ω
LVPECL
Z0=50
Ω
Z0=50
Ω
140
Ω
165
Ω
165
Ω
100
Ω
BLVDS
Z0=50
Ω
Z0=50
Ω