参数资料
| 型号： | XCV300E-8FG456C |
| 厂商： | Xilinx Inc |
| 文件页数： | 173/233页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 456-FBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB数： | 1536 |
| 逻辑元件/单元数： | 6912 |
| RAM 位总计： | 131072 |
| 输入/输出数： | 312 |
| 门数： | 411955 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 456-BBGA |
| 供应商设备封装： | 456-FBGA |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页当前第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页第221页第222页第223页第224页第225页第226页第227页第228页第229页第230页第231页第232页第233页
Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
38
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
IOB Flip-Flop/Latch Property
The Virtex-E series I/O Block (IOB) includes an optional
register on the input path, an optional register on the output
path, and an optional register on the 3-state control pin. The
design implementation software automatically takes advan-
tage of these registers when the following option for the Map
program is specified.
map –pr b <filename>
Alternatively, the IOB = TRUE property can be placed on a
register to force the mapper to place the register in an IOB.
Location Constraints
Specify the location of each SelectI/O symbol with the loca-
tion constraint LOC attached to the SelectI/O symbol. The
external port identifier indicates the value of the location
constrain. The format of the port identifier depends on the
package chosen for the specific design.
The LOC properties use the following form:
LOC=A42
LOC=P37
Output Slew Rate Property
As mentioned above, a variety of symbol names provide the
option of choosing the desired slew rate for the output buf-
fers. In the case of the LVTTL output buffers (OBUF,
OBUFT, and IOBUF), slew rate control can be alternatively
programed with the SLEW= property. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals. The SLEW=
property has one of the two following values.
SLEW=SLOW
SLEW=FAST
Output Drive Strength Property
The desired output drive strength can be additionally speci-
fied by choosing the appropriate library symbol. The Xilinx
library also provides an alternative method for specifying
this feature. For the LVTTL output buffers (OBUF, OBUFT,
and IOBUF, the desired drive strength can be specified with
the DRIVE= property. This property could have one of the
following seven values.
DRIVE=2
DRIVE=4
DRIVE=6
DRIVE=8
DRIVE=12 (Default)
DRIVE=16
DRIVE=24
Design Considerations
Reference Voltage (VREF) Pins
Low-voltage I/O standards with a differential amplifier input
buffer require an input reference voltage (VREF). Provide the
VREF as an external signal to the device.
The voltage reference signal is “banked” within the device on
a half-edge basis such that for all packages there are eight
resentation of the Virtex-E I/O banks. Within each bank
approximately one of every six I/O pins is automatically con-
figured as a VREF input. After placing a differential amplifier
input signal within a given VREF bank, the same external
source must drive all I/O pins configured as a VREF input.
Within each VREF bank, any input buffers that require a
VREF signal must be of the same type. Output buffers of any
type and input buffers can be placed without requiring a ref-
erence voltage within the same VREF bank.
Output Drive Source Voltage (VCCO) Pins
Many of the low voltage I/O standards supported by
SelectI/O devices require a different output drive source
voltage (VCCO). As a result each device can often have to
support multiple output drive source voltages.
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four VCCO banks.
Output buffers within a given VCCO bank must share the
same output drive source voltage. Input buffers for LVTTL,
LVCMOS2, LVCMOS18, PCI33_3, and PCI 66_3 use the
VCCO voltage for Input VCCO voltage.
Transmission Line Effects
The delay of an electrical signal along a wire is dominated
by the rise and fall times when the signal travels a short dis-
tance. Transmission line delays vary with inductance and
capacitance, but a well-designed board can experience
delays of approximately 180 ps per inch.
Transmission line effects, or reflections, typically start at
1.5" for fast (1.5 ns) rise and fall times. Poor (or non-exis-
tent) termination or changes in the transmission line imped-
ance cause these reflections and can cause additional
delay in longer traces. As system speeds continue to
increase, the effect of I/O delays can become a limiting fac-
tor and therefore transmission line termination becomes
increasingly more important.
Termination Techniques
A variety of termination techniques reduce the impact of
transmission line effects.
The following are output termination techniques:
None
Series
Parallel (Shunt)
Series and Parallel (Series-Shunt)
相关PDF资料 |
PDF描述 |
|---|---|
| XCV300E-7FG456I | IC FPGA 1.8V I-TEMP 456-FBGA |
| XC2V2000-4FGG676C | IC VIRTEX-II FPGA 2M 676-FBGA |
| XC5VLX50-1FFG1153C | IC FPGA VIRTEX-5 50K 1153FBGA |
| XC2V1500-4FG676I | IC FPGA VIRTEX-II 676FGBGA |
| 4-1393561-8 | CONN D-SUB CABLE BUSHING 9-37POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV300E-8FG456I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV300E-8HQ204C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virte -E 1.8 V Field Programmable Gate Arrays |
| XCV300E-8HQ204I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virte -E 1.8 V Field Programmable Gate Arrays |
| XCV300E-8HQ240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV300E-8HQ240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。