参数资料
型号: XPC850DEVR50BU
厂商: Freescale Semiconductor
文件页数: 8/72页
文件大小: 0K
描述: IC MPU POWERQUICC 50MHZ 256-PBGA
标准包装: 60
系列: MPC8xx
处理器类型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
电压: 3.3V
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-PBGA(23x23)
包装: 托盘
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
16
Freescale Semiconductor
Bus Signal Timing
B31
CLKOUT falling edge to CS
valid - as requested by control
bit CST4 in the corresponding
word in the UPM
1.50
6.00
1.50
6.00
1.50
6.00
50.00
ns
B31a
CLKOUT falling edge to CS
valid - as requested by control
bit CST1 in the corresponding
word in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B31b
CLKOUT rising edge to CS valid
- as requested by control bit
CST2 in the corresponding
word in the UPM
1.50
8.00
1.50
8.00
1.50
8.00
50.00
ns
B31c
CLKOUT rising edge to CS valid
- as requested by control bit
CST3 in the corresponding
word in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B31d
CLKOUT falling edge to CS
valid - as requested by control
bit CST1 in the corresponding
word in the UPM EBDF = 1
9.00
14.00 13.00 18.00
11.00
16.00
0.375
50.00
ns
B32
CLKOUT falling edge to BS
valid - as requested by control
bit BST4 in the corresponding
word in the UPM
1.50
6.00
1.50
6.00
1.50
6.00
50.00
ns
B32a
CLKOUT falling edge to BS
valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 0
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B32b
CLKOUT rising edge to BS valid
- as requested by control bit
BST2 in the corresponding
word in the UPM
1.50
8.00
1.50
8.00
1.50
8.00
50.00
ns
B32c
CLKOUT rising edge to BS valid
- as requested by control bit
BST3 in the corresponding
word in the UPM
5.00
12.00
8.00
14.00
6.00
13.00
0.250
50.00
ns
B32d
CLKOUT falling edge to BS
valid - as requested by control
bit BST1 in the corresponding
word in the UPM, EBDF = 1
9.00
14.00 13.00 18.00
11.00
16.00
0.375
50.00
ns
B33
CLKOUT falling edge to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
1.50
6.00
1.50
6.00
1.50
6.00
50.00
ns
Table 6. Bus Operation Timing 1 (continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
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