参数资料
型号: XR17C158CV-F
厂商: Exar Corporation
文件页数: 21/67页
文件大小: 0K
描述: IC UART PCI BUS 5V OCTAL 144LQFP
产品培训模块: UART Product Overview
标准包装: 60
特点: *
通道数: 8
FIFO's: 64 字节
规程: RS485
电源电压: 4.5 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
其它名称: 1016-1287
XR17C158
xr
5V PCI BUS OCTAL UART
REV. 1.4.3
28
4.2
Transmitter
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enabled, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
4.2.1
Transmit Holding Register (THR) - Write-Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (bit-0) becomes the first data bit to go out. The THR is also
the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
4.2.2
Transmitter Operation in non-FIFO mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
OUTPUT Data Rate
MCR Bit-7=1
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
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