参数资料
型号: XR17V352IB113-F
厂商: Exar Corporation
文件页数: 1/64页
文件大小: 0K
描述: IC UART PCIE 256B DUAL 113FPBGA
产品培训模块: PCIe UARTs
标准包装: 260
特点: *
通道数: 2,DUART
FIFO's: 256 字节
规程: RS485
电源电压: 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 113-LFBGA
供应商设备封装: 113-FPBGA
包装: 托盘
其它名称: 1016-1471
XR17V352IB113-F-ND
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
APRIL 2012
REV. 1.0.3
GENERAL DESCRIPTION
The XR17V3521 (V352) is a single chip 2-channel
PCI Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The V352 serves as a
single lane PCIe bridge to 2 indepedent enhanced
16550 compatible UARTs. The V352 is compliant to
PCIe 2.0 Gen 1 (2.5GT/s).
In addition to the UART channels, the V352 has 16
multi-purpose I/Os (MPIOs), a 16-bit general purpose
counter/timer and a global interrupt status register to
optimize interrupt servicing.
Each UART of the V352 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
25Mbps. The V352 is available in a 113-pin FPBGA
package (9 x 9 mm).
NOTE 1: Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
APPLICATIONS
Next generation Point-of-Sale Systems
Remote Access Servers
Storage Network Management
Factory Automation and Process Control
Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
Single 3.3V power supply
Internal buck regulator for 1.2V core
PCIe 2.0 Gen 1 compliant
x1 Link, dual simplex, 2.5Gbps in each direction
EEPROM interface for configuration
Data read/write 32-bit operation
Global interrupt status register for both UARTs
Up to 25 Mbps serial data rate
16 multi-purpose inputs/outputs (MPIOs)
16-bit general purpose timer/counter
Sleep mode with wake-up Indicator
Two independent UART channels controlled with
16550 compatible register Set
256-byte TX and RX FIFOs
Programmable TX and RX Trigger Levels
TX/RX FIFO Level Counters
Fractional baud rate generator
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
Automatic Xon/Xoff software flow control
RS-485 half duplex direction control output
with programmable turn-around delay
Multi-drop with Auto Address Detection
Infrared (IrDA 1.1) data encoder/decoder
Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
FIGURE 1. BLOCK DIAGRAM OF THE XR17V352
G loba l
C onfigur a tion
R eg ister s
C r ystal O s c/B u ffer
P C I L o cal
Bu s
In te r fa c e
C o nfigur a tion
Sp a c e
R eg ister s
-
In puts /O utputs
16-b it
Tim e r/C ounte r
UA RT Ch a n n e l 0
6 4 - b y te TX FIFO
6 4 - by te R X F IFO
BR G
IR
E NDE C
T X & RX
U ART
Re g s
TX +
RX +
EE C K
EE D O
EE C S
UA RT Ch a n n e l 2
UA RT Ch a n n e l 5
UA RT Ch a n n e l 6
TM R C K
RX[7 :0 ]
T X [7 :0 ]
EE PRO M
In ter face
G loba l
C onfigur a tion
R eg ister s
G loba l
C onfigur a tion
R eg ister s
PCIe
In ter face
C o nfigur a tion
Sp a c e
R eg ister s
Mu lti-p u rp o s e
Inputs /O utputs
16
16 - bit
Tim e r/C ounte r
UA RT Ch a n n e l 0
6 4 - b y te TX FIFO
64-
BR G
IR
E NDE C
T X & RX
U ART
Re g s
UAR T Ch a n n e l 0
256-b yte T X F IF O
BRG
IR
EN D EC
TX & R X
UART
Re g s
EE D I
TM R C K
R X [1 :0 ]
T X [1 :0 ]
R T S # [1 :0 ]
DT R# [1 :0 ]
C T S # [1 :0 ]
D S R # [1 :0 ]
D C D #[1 :0]
MP IO [1 5 :0 ]
R I#[1 :0]
EN IR #
EE PRO M
In ter face
EE PRO M
In ter face
256-b y te R X F IF O
TX -
RX -
CL K+
CL K-
CL KRE Q #
RS T #
E N 485#
B uc k R e gula tor
125 M H z C lo ck
UART C h a n n e l 1
2 5 6-b y te TX FIFO
BRG
IR
E NDE C
T X & RX
UA RT
Re g s
256-b yte R X F IF O
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