参数资料
型号: XR17V352IB113-F
厂商: Exar Corporation
文件页数: 5/64页
文件大小: 0K
描述: IC UART PCIE 256B DUAL 113FPBGA
产品培训模块: PCIe UARTs
标准包装: 260
特点: *
通道数: 2,DUART
FIFO's: 256 字节
规程: RS485
电源电压: 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 113-LFBGA
供应商设备封装: 113-FPBGA
包装: 托盘
其它名称: 1016-1471
XR17V352IB113-F-ND
XR17V352
13
REV. 1.0.3
HIGH PERFORMANCE DUAL PCI EXPRESS UART
1.3
Device Internal Register Sets
The Device Configuration Registers and the two individual UART Configuration Registers of the V352
occupy 2K of PCI bus memory address space. These addresses are offset onto the basic memory address, a
value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. The
UART Configuration Registers are mapped into 2 address blocks where each UART channel occupies 1024
bytes memory space for its own registers that include the 16550 compatible registers. The Device
Configuration Registers are accessible from both UART channels. However, not all bits can be controlled by
both channels. The UART channel can only control the 8XMODE, 4XMODE, RESET and SLEEP register bits
that apply to that particular channel. For example, this prevents channel 0 from accidentally resetting channel
1.
All these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address given by the
host at the beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32
bits format in special locations given in the Table 4 below. Every time a read or write operation is made to the
transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location
either in byte, word or DWORD. One special case applies to the receive data unloading when reading the
receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to
maintain integrity of the data byte with its associated error flags. These special registers are further discussed
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