参数资料
型号: XRM48L950ZWTT
厂商: Texas Instruments
文件页数: 160/176页
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
标准包装: 1
系列: Hercules™ ARM® RM4x
应用: 工业安全,医疗
核心处理器: ARM? Cortex? - R4F
程序存储器类型: 闪存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太网,I²C,LIN,MibSPI,SCI,SPI,USB
输入/输出数: 120
电源电压: 1.14 V ~ 3.6 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 337-LFBGA
包装: 托盘
供应商设备封装: 337-NFBGA(16x16)
其它名称: 296-29390
EVEN Address
TCMBUS
ODD Address
TCMBUS
64Bitdatabus
Upper32bits data&
4ECCbits
Lower 32bits data&
4ECCbits
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
Upper32bits data&
4ECCbits
Lower 32bits data&
4ECCbits
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
36Bit
wide
RAM
TCRAM
Interface1
PMT I/F
VBUSP I/F
CortexR4F
B0
TCM
B1
TCM
A
TCM
TCRAM
Interface2
PMT I/F
VBUSP I/F
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.11 Tightly-Coupled RAM Interface Module
Figure 4-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F CPU.
Figure 4-10. TCRAM Block Diagram
4.11.1 Features
The features of the Tightly Coupled RAM (TCRAM) Module are:
Acts as slave to the Cortex-R4F CPU's BTCM interface
Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
Monitors CPU Event Bus and generates single or multi-bit error interrupts
Stores addresses for single and multi-bit errors
Supports RAM trace module
Provides CPU address bus integrity checking by supporting parity checking on the address bus
Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved
RAM banks and generating independent RAM access control signals to the two banks
Supports auto-initialization of the RAM banks along with the ECC bits
4.11.2 TCRAMW ECC Support
The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. It also
stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The
TCRAMW monitors the CPU's event bus and provides registers for indicating single/multi-bit errors and
also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC
checking for the RAM accesses must be enabled inside the CPU.
For more information see the device specific technical reference manual.
4.12
Parity Protection for peripheral RAMs
Most peripheral RAMs are protected by odd/even parity checking. During a read access the parity is
calculated based on the data read from the peripheral RAM and compared with the good parity value
stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a
parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral
RAM address that caused the parity error.
84
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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