参数资料
型号: XRM48L950ZWTT
厂商: Texas Instruments
文件页数: 29/176页
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
标准包装: 1
系列: Hercules™ ARM® RM4x
应用: 工业安全,医疗
核心处理器: ARM? Cortex? - R4F
程序存储器类型: 闪存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太网,I²C,LIN,MibSPI,SCI,SPI,USB
输入/输出数: 120
电源电压: 1.14 V ~ 3.6 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 337-LFBGA
包装: 托盘
供应商设备封装: 337-NFBGA(16x16)
其它名称: 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
Table 5-4. Alternate MIBADC1 Event Trigger Hookup (continued)
Event #
Source Select Bits for G1, G2 or Event
Trigger
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
3
010
N2HET1[27]
4
011
RTI compare 0 interrupt
5
100
N2HET1[17]
6
101
N2HET1[19]
7
110
N2HET1[11]
8
111
N2HET2[13]
The selection between the default MIBADC1 event trigger hook-up versus the alternate event trigger hook-
up is done by multiplexing control module register 30 bits 0 and 1.
If 30[0] = 1, then the default MibADC1 event trigger hook-up is used.
If 30[0] = 0 and 30[1] = 1, then the alternate MibADC1 event trigger hook-up is used.
NOTE
For ADEVT trigger source, the connection to the MibADC1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
configuring ADEVT as an output function on to the pad (via the mux control), or by driving
the ADEVT signal from an external trigger source as input. If the mux control module is used
to select different functionality instead of the ADEVT signal, then care must be taken to
disable ADEVT from triggering conversions; there is no multiplexing on the input connection.
NOTE
For N2HETx trigger sources, the connection to the MibADC1 module trigger input is made
from the input side of the output buffer (at the N2HETx module boundary). This way, a
trigger condition can be generated even if the N2HETx signal is not selected to be output on
the pad.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
5.2.2.3
Default MIBADC2 Event Trigger Hookup
Table 5-5. MIBADC2 Event Trigger Hookup
Event #
Source Select Bits for G1, G2 or Event
Trigger
(G1SRC[2:0], G2SRC[2:0] or EVSRC[2:0])
1
000
AD2EVT
2
001
N2HET1[8]
3
010
N2HET1[10]
4
011
RTI compare 0
5
100
N2HET1[12]
6
101
N2HET1[14]
7
110
GIOB[0]
8
111
GIOB[1]
124
Peripheral Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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