参数资料
型号: XRM48L950ZWTT
厂商: Texas Instruments
文件页数: 27/176页
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 337NFBGA
标准包装: 1
系列: Hercules™ ARM® RM4x
应用: 工业安全,医疗
核心处理器: ARM? Cortex? - R4F
程序存储器类型: 闪存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太网,I²C,LIN,MibSPI,SCI,SPI,USB
输入/输出数: 120
电源电压: 1.14 V ~ 3.6 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 337-LFBGA
包装: 托盘
供应商设备封装: 337-NFBGA(16x16)
其它名称: 296-29390
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
5
Peripheral Information and Electrical Specifications
5.1
Peripheral Legend
Table 5-1. Peripheral Legend
Abbreviation
Full Name
MibADC
Analog To Digital Converter
CCM-R4F
CPU Compare Module - CortexR4F
CRC
Cyclic Redundancy Check
DCAN
Controller Area Network
DCC
Dual Clock Comparator
DMA
Direct Memory Access
DMM
Data Modification Module
EMIF
External Memory Interface
ESM
Error Signaling Module
ETM-R4F
Embedded Trace Macrocell - CortexR4F
GPIO
General-Purpose Input/Output
HTU
High End Timer Transfer Unit
I2C
Inter-Integrated Circuit
LIN
Local Interconnect Network
MIBSPI
Multibuffer Serial Peripheral Interface
N2HET
Platform High-End Timer
POM
Parameter Overlay Module
RTI
Real-Time Interrupt Module
RTP
RAM Trace Port
SCI
Serial Communications Interface
SPI
Serial Peripheral Interface
USB
Universal Serial Bus
VIM
Vectored Interrupt Manager
5.2
Multi-Buffered 12bit Analog-to-Digital Converter
The multibuffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that
enhances the A-to-D performance by preventing digital switching noise on the logic circuitry which could
be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given
with respect to ADREFLO unless otherwise noted.
Table 5-2. MibADC Overview
Description
Value
Resolution
12 bits
Monotonic
Assured
Output conversion code
00h to FFFh [00 for VAI ≤ ADREFLO; FFF for VAI ≥ ADREFHI]
5.2.1
Features
10-/12-bit resolution
ADREFHI and ADREFLO pins (high and low reference voltages)
Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK
One memory region per conversion group is available (event, group 1, group 2)
Allocation of channels to conversion groups is completely programmable
Memory regions are serviced either by interrupt or by DMA
122
Peripheral Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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