参数资料
| 型号： | XRT71D00IQ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 23/26页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATTENUATOR SGL 32TQFP |
| 标准包装： | 250 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
XRT71D00
á
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
5
10
ClkES/(SDI)
I
Clock Edge Select Input/Serial Data Input Pin.
The function of this pin depends on whether XRT71D00 is configured in Harware or
Host Mode.
Hardware Mode—Clock Edge Select Input
This input pin permits the user to do the following.
1. To configure the XRT71D00 device to latch the data, on the RPOS and
RNEG input pin, upon either the rising or falling edge of the RCLK input
signal.
2. To configure the XRT71D00 device to update the data, which is output via
the “RRPOS” and “RRNEG” pins, upon either the rising or falling edge of
the RRCLK output signal.
Setting this input pin LOW configures the XRT71D00 device to do the following.
1. Sample and latch the RPOS and RNEG input signals upon the rising edge
of the RCLK input signal.
2. Update the data, output via the RRPOS and RRNEG output pins, upon
the falling edge of the RRCLK output signal.
Conversely, setting this input pin HIGH configures the XRT71D00 device to do the fol-
lowing.
1. Same and latch the RPOS and RNEG input signals upon the falling edge
of the RCLK input signal.
2. Update the data, output via the RRPOS and RRNEG output pins, upon
the rising edge of the RRCLK output signal.
Host Mode—Serial Data Input
When the Microprocessor/Microcontroller is executing a READ operation, with the
Microprocessor Serial Interface (of the XRT71D00 device) then it is expected to apply
the address value (of the “Target” Command Register) to this input pin, in a serial man-
ner.
When the Microprocessor/Microcontroller is executing a WRITE operation, with the
Microprocessor Serial Interface, then it is expected to do the following.
1. Apply the address value (of the “Target” Command Register) to this input
pin, in a serial manner.
2. Apply the data (to be written into the “Target” Command Register) to this
input pin.
NOTE: A detailed description on how to read and write data into the Command Regis-
ters of the XRT71D00 device (via the Microprocessor Serial Interface) is presented in
Section _.
11
FSS/(SClk)
I
FIFO Size Select Input/Serial Clock Input.
The function of this input pin depends on whether XRT71D00 is configured in Hard-
ware or Host mode.
Hardware Mode—FIFO Size Select Input
This input pin permits the user to select the operating depth of the “on-chip” FIFO.
When high: Selects 32 bits FIFO.
When low: Selects 16 bits FIFO.
NOTE: For SONET De-synchronizer applications, the user is advised to configure the
FIFO Depth to 32 bits.
Host Mode—Microprocessor Serial Interface Clock Signal
This signal will be used to sample the data, on the SDI pin, on the rising edge of this
signal. Additionally, during “Read” operations, the Microprocessor Serial Interface will
update the SDO output on the falling edge of this signal.
PIN DESCRIPTION
PIN #NAME
TYPE
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT71D00IQTR-F | 功能描述:时钟合成器/抖动清除器 DS3/E3/STS-1Jit Attn 3.3/5.0V 1 CH 1 CHIP RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03 | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03ES | 功能描述:时钟合成器/抖动清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03IV | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03IV-F | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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