参数资料
| 型号： | XRT71D00IQ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 5/26页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATTENUATOR SGL 32TQFP |
| 标准包装： | 250 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
12
SYSTEM DESCRIPTION
The XRT71D00 is a fully integrated and self-contained
DS3, E3 and STS-1 Jitter Attenuator IC which was de-
signed to function as either a “Jitter Attenuator” or as a
“Clock Smoother” within SONET De-Synchronizer ap-
plications.
More specifically, the XRT71D00 device was de-
signed to do the following.
1. To attenuate the Jitter (of the incoming clock and
data) such that the user’s system will comply with
the following jitter transfer characteristic require-
ments.
ETSI TBR-24 (for E3 applications)
ITU-T G.751 (for E3 applications)
ITU-T G.752 (for E3 applications)
ITU-T G.755 (for E3 applications)
Bellcore GR-499-CORE (Category I to Category
II Interface Jitter Transfer Characteristic require-
ments for DS3 applications).
Bellcore GR-253-CORE (for SONET STS-1 appli-
cations)
2. To receive the gapped 51.84MHz clock and data
signals, from an “OC-N to DS3 Mapper/De-Map-
per” IC; and to smooth these signals to an “un-
gapped” 44.736MHz clock and data signals. This
particular application is often referred to as a
“SONET De-synchronizer” application. In this
application, the “smoothed” RRCLK and RRPOS
signals could (potentially) be routed to a DS3 LIU
IC, for transmission to a remote terminal equip-
ment, over coaxial cable.
In addition, the XRT71D00 also meets both the “map-
ping” and “pointer adjustment” jitter generation crite-
ria for both Category I and Category II interfaces as
specified in Bellcore GR-253.
The XRT71D00 also meets the DS3 wander specifi-
cation that apply to SONET and asynchronous inter-
faces as specified in the ANSI T1.105.03b 1997 stan-
dard.
Figure 5 presents a simple block diagram of the
XRT71D00 device, when it is configured to operate in
the “Hardware” Mode. Likewise Figure 6 presents a
simple block diagram of the XRT71D00 device, when
it is configured to operate in the “Host” Mode.
FIGURE 5. ILLUSTRATION OF THE XRT71D00 (CONFIGURED TO OPERATE IN THE “HARDWARE” MODE)
16/32 Bit FIFO
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRClk
RRPOS
RRNEG
FL
DJA
RClk
ClkES
RPOS
RNEG
BWS
ICT
MClk
Jittery
Clock
Smoothed
Clock
FSS
HOST/HW
Reset
E3/DS3
相关PDF资料 |
PDF描述 |
|---|---|
| XRT71D03IV-F | IC JITTER ATTENUATOR 3CH 64TQFP |
| XRT71D04IV | IC JITTER ATTENUATOR 4CH 80TQFP |
| XRT8000IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| XRT8001IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| XRT8010IL-F | IC CLK MULTIPLR LVDS 16QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT71D00IQTR-F | 功能描述:时钟合成器/抖动清除器 DS3/E3/STS-1Jit Attn 3.3/5.0V 1 CH 1 CHIP RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03 | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03ES | 功能描述:时钟合成器/抖动清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03IV | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03IV-F | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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