参数资料
| 型号： | XRT71D00IQ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 7/26页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATTENUATOR SGL 32TQFP |
| 标准包装： | 250 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
14
1.3.1
Jitter Tolerance:
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming sig-
nal that it can receive in an “error-free”manner.
1.3.2
Jitter Generation:
Jitter generation is defined in Section 7.3.3 of GR-
499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of “map-
ping” and “pointer adjustment” jitter generation.
Mapping jitter is the sum of the intrinsic payload map-
ping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchro-
nous DSn mapping into STS SPE.
1.3.3
Jitter Attenuation:
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the refer-
ence clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
beled “Smoothed Clock”. This “Smoothed Clock” is
now used to “Read Out” the “Recovered Data” from
the 16/32 bit FIFO. This “Smoothed Clock” will also
be output to the Terminal Equipment via the “RRClk”
output pin. Likewise, the “Smoothed Recovered Data”
will output to the Terminal Equipment via the RRPOS
and RRNEG output pins.
The XRT71D00 device is designed to work as a com-
panion device with XRT73L00 (STS-1/DS3/E3) Line
Interface Unit.
ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when mea-
sured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compli-
ant with the standard. ITU G.751 is another applica-
tion where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multi-
plexer system.
1.4
XRT71D00 JITTTER TRANSFER CHARACTERIS-
TICS
transfer characteristics testing, performed on the
FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK
0.1
Jitter
Gain
(dB)
Acceptable
Range
40
Frequency (Hz)
slope = -20 dB/decade
相关PDF资料 |
PDF描述 |
|---|---|
| XRT71D03IV-F | IC JITTER ATTENUATOR 3CH 64TQFP |
| XRT71D04IV | IC JITTER ATTENUATOR 4CH 80TQFP |
| XRT8000IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| XRT8001IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| XRT8010IL-F | IC CLK MULTIPLR LVDS 16QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT71D00IQTR-F | 功能描述:时钟合成器/抖动清除器 DS3/E3/STS-1Jit Attn 3.3/5.0V 1 CH 1 CHIP RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03 | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03ES | 功能描述:时钟合成器/抖动清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03IV | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03IV-F | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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