参数资料
| 型号： | XRT71D00IQ-F |
| 厂商： | Exar Corporation |
| 文件页数： | 6/26页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATTENUATOR SGL 32TQFP |
| 标准包装： | 250 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 托盘 |
XRT71D00
á
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
13
The XRT71D00 DS3/E3/STS-1 Jitter Attenuator IC
consists of the following functional blocks:
Jitter Attenuator Phase Locked Loop(PLL)
Timing Control
2-Channel 16/32 Bit FIFO.
Microprocessor Serial Interface
1.0
THE JITTER ATTENUATOR PLL
The Jitter Attenuator PLL is a narrow-band PLL that
accepts a “jittery” clock signal via the RCLK input pin.
The Jitter Attenuator PLL locks onto the RCLK input
signal and synthesizes a “same-rate” signal. As the
Jitter Attenuator PLL synthesizes this signal, it elimi-
nates much of the jitter that exists within the RCLK in-
put signal. The resulting smoothed clock signal is
then output via the “RRCLK” output signal.
1.1
THE JITTER TRANSFER CHARACTERISTICS OF THE
JITTER ATTENUATOR PLL
The Jitter Transfer Characteristics of the XRT71D00
device is ultimately dictated by the Jitter Transfer
Characteristics of the Jitter Attenuator PLL. The Jitter
Transfer Characteristics of the Jitter Attenuator PLL is
dictated by the following variables.
1. The operating mode/data rate of the XRT71D00
device.
2. The setting of the BWS (Bandwidth Select) input
pin or bit-field.
1.2
DEFINITION OF JITTER
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as “short term
variations of the significant instants of a digita signal
from their ideal positions in time”. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.3
JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
FIGURE 6. ILLUSTRATION OF THE XRT71D00 (CONFIGURED TO OPERATE IN THE “HOST” MODE)
HOST/HW
Reset
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRClk
RRPOS
RRNEG
FL
RClk
RPOS
RNEG
ICT
CS
SDI
SDO
SClk
MClk
Smoothed
Clock
Jittery Clock
相关PDF资料 |
PDF描述 |
|---|---|
| XRT71D03IV-F | IC JITTER ATTENUATOR 3CH 64TQFP |
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| XRT8000IP-F | IC WAN CLOCK E1/E1 DUAL 18PDIP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT71D00IQTR-F | 功能描述:时钟合成器/抖动清除器 DS3/E3/STS-1Jit Attn 3.3/5.0V 1 CH 1 CHIP RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03 | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03ES | 功能描述:时钟合成器/抖动清除器 3CH T3/E3JA w/T73LC03A RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT71D03IV | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR |
| XRT71D03IV-F | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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