参数资料
型号: XRT73LC00AIV-F
厂商: Exar Corporation
文件页数: 55/61页
文件大小: 0K
描述: IC LIU STS1/DS3/E3 SGL 44TQFP
标准包装: 160
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 44-LQFP
供应商设备封装: 44-TQFP(10x10)
包装: 托盘
XRT73LC00A
56
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
CS
-
Chip Select (Active Low)
SCLK
-
Serial Clock
SDI
-
Serial Data Input
SDO
-
Serial Data Output
Using the Microprocessor Serial Interface
The following instructions for using the Microprocessor Serial Interface are best understood by referring to the
diagram in Figure 34.
In order to use the Microprocessor Serial Interface, a clock signal must be supplied to the SCLK input pin. A
Read or Write operation can then be initiated by asserting the active-low Chip Select input pin (CS). It is
important to assert the CS pin (e.g., toggle it “Low”) at least 5ns prior to the very first rising edge of the clock
signal.
Once the CS input pin has been asserted, the type of operation and the target register address must now be
specified. This information is supplied to the Microprocessor Serial Interface by writing eight serial bits of data
into the SDI input.
NOTE: Each of these bits is clocked into the SDI input on the rising edge of SCLK. These eight bits are identified and
described below.
Bit 1 - R/W (Read/Write) Bit
This bit is clocked into the SDI input on the first rising edge of SCLK after CS has been asserted. This bit
indicates whether the current operation is a Read or Write operation.
A “1” in this bit specifies a Read
operation, a “0” in this bit specifies a Write operation.
Bits 2 through 5: The four (4) bit Address Values (labeled A0, A1, A2 and A3)
The next four rising edges of the SCLK signal clock in the 4-bit address value for this particular Read (or Write)
operation. The address selects the Command Register in the XRT73LC00A that the user is either reading data
from or writing data to. The address bits must be supplied to the SDI input pin in ascending order with the LSB
(least significant bit) first.
Bits 6 and 7:
The next two bits, A4 and A5 must be set to “0” as shown in Figure 34.
Bit 8:
The value of A6 is a “don’t care”.
FIGURE 34. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
D0
D1
D2
D7
D6
D5
D4
D3
High Z
SDO
A0
D0
R/W
D1
A6
0
A3
A2
A1
D7
D6
D5
D4
D3
D2
SDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SClk
CS
High Z
- Denotes a “don’t care” value
A4 and A5 are always “0”.
R/W = “1” for “Read” Operations
R/W = “0” for “Write” Operations
Notes:
- Denotes a “don’t care” value
A4 and A5 are always “0”.
R/W = “1” for “Read” Operations
R/W = “0” for “Write” Operations
Notes:
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